Abstract: A semiconductor device includes a substrate and a contact pad over the substrate. The semiconductor device further includes a conductive via electrically connected to the contact pad. The conductive via includes a conductive via layer having a first thickness, and a first conductive layer, wherein the first conductive layer is between the contact pad and the conductive via layer. The semiconductor device further includes a conductive pillar electrically connected to the conductive via. The conductive pillar includes a conductive pillar layer having a second thickness, and a second conductive layer having outer edges substantially aligned with outer edges of the conductive pillar layer, wherein the second conductive layer is between the conductive via layer and the conductive pillar layer. A ratio of the first thickness to the second thickness ranges from about 0.33 to about 0.55.

Abstract: A semiconductor device includes a substrate and a contact pad over the substrate. The semiconductor device further includes a conductive via electrically connected to the contact pad. The conductive via includes a conductive via layer having a first thickness, and a first conductive layer, wherein the first conductive layer is between the contact pad and the conductive via layer. The semiconductor device further includes a conductive pillar electrically connected to the conductive via. The conductive pillar includes a conductive pillar layer having a second thickness, and a second conductive layer having outer edges substantially aligned with outer edges of the conductive pillar layer, wherein the second conductive layer is between the conductive via layer and the conductive pillar layer. A ratio of the first thickness to the second thickness ranges from about 0.33 to about 0.55.

Abstract: A method for fabricating a semiconductor device includes forming a first photo-sensitive layer over a contact pad, wherein the contact pad is on a substrate. The method further includes patterning the first photo-sensitive layer to form a first opening over a portion of the contact pad. The method further includes plating a conductive via in the first opening; and removing the first photo-sensitive layer. The method further includes forming a passivation layer over the substrate, contact pad, and conductive via, and exposing the conductive via by grinding the passivation layer. The method further includes forming a second photo-sensitive layer over the conductive via and passivation layer. The method further includes patterning the second photo-sensitive layer to form a second opening larger than and completely exposing the conductive via. The method further includes plating a conductive pillar in the second opening; and removing the second photo-sensitive layer.

Abstract: A package includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis, wherein the first work piece is rigid, and an entirety of the metal trace is on the first work piece. The package further includes a second work piece with a plurality of elongated bumps, wherein at least one of the plurality of elongated metal bumps has a second axis and at least another of the plurality of elongated metal bumps has a third axis, wherein the second and the third axes are not the same and the second axis is at a non-zero angle from the first axis, wherein the plurality of elongated bumps are electrically connected to the metal trace.

Abstract: A method for fabricating a semiconductor device includes forming a first photo-sensitive layer over a contact pad, wherein the contact pad is on a substrate. The method further includes patterning the first photo-sensitive layer to form a first opening over a portion of the contact pad. The method further includes plating a conductive via in the first opening; and removing the first photo-sensitive layer. The method further includes forming a passivation layer over the substrate, contact pad, and conductive via, and exposing the conductive via by grinding the passivation layer. The method further includes forming a second photo-sensitive layer over the conductive via and passivation layer. The method further includes patterning the second photo-sensitive layer to form a second opening larger than and completely exposing the conductive via. The method further includes plating a conductive pillar in the second opening; and removing the second photo-sensitive layer.

Abstract: The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate and having an opening with a first width over the contact pad; a conductive via within the opening; and a conductive pillar having a second width completely covering the conductive via, wherein a ratio of the first width to the second width is from about 0.15 to 0.55.

Abstract: A package includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis, wherein the first work piece is rigid, and an entirety of the metal trace is on the first work piece. The package further includes a second work piece with a plurality of elongated bumps, wherein at least one of the plurality of elongated metal bumps has a second axis and at least another of the plurality of elongated metal bumps has a third axis, wherein the second and the third axes are not the same and the second axis is at a non-zero angle from the first axis, wherein the plurality of elongated bumps are electrically connected to the metal trace.

Abstract: A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

Abstract: A device includes a work piece, and a metal trace on a surface of the work piece. A Bump-on-Trace (BOT) is formed at the surface of the work piece. The BOT structure includes a metal bump, and a solder bump bonding the metal bump to a portion of the metal trace. The metal trace includes a metal trace extension not covered by the solder bump.

Abstract: A method comprises determining a warpage of an integrated circuit (IC) package design. The IC package design includes a substrate having a top solder mask on a first major surface and a bottom solder mask on a second major surface opposite the first major surface. The first major surface has an IC die mounted over the top solder mask. The design is modified, including modifying an average thickness of one of the group consisting of the top solder mask and the bottom solder mask, so as to reduce the warpage. An IC package is fabricated according to the modified design.

Abstract: A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

Abstract: The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate and having an opening with a first width over the contact pad; a conductive via within the opening; and a conductive pillar having a second width completely covering the conductive via, wherein a ratio of the first width to the second width is from about 0.15 to 0.55.

Abstract: A method comprises determining a warpage of an integrated circuit (IC) package design. The IC package design includes a substrate having a top solder mask on a first major surface and a bottom solder mask on a second major surface opposite the first major surface. The first major surface has an IC die mounted over the top solder mask. The design is modified, including modifying an average thickness of one of the group consisting of the top solder mask and the bottom solder mask, so as to reduce the warpage. An IC package is fabricated according to the modified design.

Abstract: The embodiments of bump-on-trace (BOT) structures and their layout on a die described reduce stresses on the dielectric layer on the metal pad and on the metal traces of the BOT structures. By orienting the axes of the metal bumps away from being parallel to the metal traces, the stresses can be reduced, which can reduce the risk of delamination of the metal traces from the substrate and the dielectric layer from the metal pad. Further, the stresses of the dielectric layer on the metal pad and on the metal traces may also be reduced by orienting the axes of the metal traces toward the center of the die. As a result, the yield can be increased.

Abstract: The embodiments of bump-on-trace (BOT) structures and their layout on a die described reduce stresses on the dielectric layer on the metal pad and on the metal traces of the BOT structures. By orienting the axes of the metal bumps away from being parallel to the metal traces, the stresses can be reduced, which can reduce the risk of delamination of the metal traces from the substrate and the dielectric layer from the metal pad. Further, the stresses of the dielectric layer on the metal pad and on the metal traces may also be reduced by orienting the axes of the metal traces toward the center of the die. As a result, the yield can be increased.

Abstract: A device includes a work piece, and a metal trace on a surface of the work piece. A Bump-on-Trace (BOT) is formed at the surface of the work piece. The BOT structure includes a metal bump, and a solder bump bonding the metal bump to a portion of the metal trace. The metal trace includes a metal trace extension not covered by the solder bump.