Abstract: A cyclic deposition and etch method is provided. The method includes depositing an epitaxial layer over a substrate at a first temperature and etching a portion of the deposited epitaxial layer at a variable temperature higher than the first temperature. The step of etching is performed while varying the temperature.

Abstract: A cyclic deposition and etch method is provided. The method includes depositing an epitaxial layer over a substrate at a first temperature and etching a portion of the deposited epitaxial layer at a variable temperature higher than the first temperature. The step of etching is performed while varying the temperature.

Abstract: A method for the improved electroplating of copper onto a copper seed layer provides burnishing the surface of the copper seed layer. The burnishing treatment is used to enhance the platability of the copper seed layer. The burnishing may be a reverse electroplating or a sputter etching process. Following the burnishing of the seed layer, the copper layer that is electroplated onto the seed layer exhibits improved quality.

Abstract: A method for the improved electroplating of copper onto a copper seed layer provides treating the surface of a copper seed layer with nitrogen or another anaerobic gas. In another aspect, a burnishing treatment is used to enhance the platability of the copper seed layer. According to another aspect, the seed layer is annealed either at an elevated temperature or for an extended time at room temperature. According to another aspect, the seed layer surface is exposed to a chemical solution that includes a surfactant, chemicals that dissolve contaminants, or both. In another aspect, the deposition of the copper seed layer may be tailored to produce a surface morphology more suited to electroplating. Following the treatment of the seed layer, the copper layer that is electroplated onto the seed layer exhibits improved quality.

Abstract: A method for monitoring copper film quality and for evaluating the annealing efficiency of a copper annealing process includes measuring hardness of a copper film formed on a substrate before and after annealing and comparing the hardness measurement results. The measurements can be correlated to grain boundary saturation levels, copper grain sizes and therefore conductivity. Hardness measurements may be taken at a plurality of locations throughout the substrate to account for variations in the copper film grain structure.

Abstract: A method for the improved electroplating of copper on to a copper seed layer provides treating the surface of a copper seed layer with nitrogen or another anaerobic gas. In another aspect, a burnishing treatment is used to enhance the platability of the copper seed layer. According to another aspect, the seed layer is annealed either at an elevated temperature or for an extended time at room temperature. According to another aspect, the seed layer surface is exposed to a chemical solution that includes a surfactant, chemicals that dissolve contaminants, or both. In another aspect, the deposition of the copper seed layer may be tailored to produce a surface morphology more suited to electroplating. Following the treatment of the seed layer, the copper layer that is electroplated onto the seed layer exhibits improved quality.

Abstract: A method for monitoring copper film quality and for evaluating the annealing efficiency of a copper annealing process includes measuring hardness of a copper film formed on a substrate before and after annealing and comparing the hardness measurement results. The measurements can be correlated to grain boundary saturation levels, copper grain sizes and therefore conductivity. Hardness measurements may be taken at a plurality of locations throughout the substrate to account for variations in the copper film grain structure.

Abstract: A method for reducing wafer surface scratching in a metal CMP process including providing a semiconductor wafer having a process surface comprising a blanket deposited metal layer; dry etching in an etchback process comprising a fluorine containing etching chemistry to remove at least a portion of the metal layer forming a metal and fluorine containing etching residue at the process surface; cleaning the process surface with a hydrofluoric acid (HF) containing cleaning solution; and carrying out a subsequent metal chemical mechanical polishing (CMP) process.

Abstract: A method of fabricating an interconnect structure, including providing a semiconductor substrate having a first conductive layer thereon, and forming a dielectric layer overlying the semiconductor substrate and the first conductive layer. An opening is formed in the dielectric layer extending to the first conductive layer. A portion of the first conductive layer is removed through the opening to form a recess having a substantially curvilinear profile. The opening and the recess are filled with a second conductive layer.

Abstract: A method for reducing wafer surface scratching in a metal CMP process including providing a semiconductor wafer having a process surface comprising a blanket deposited metal layer; dry etching in an etchback process comprising a fluorine containing etching chemistry to remove at least a portion of the metal layer forming a metal and fluorine containing etching residue at the process surface; cleaning the process surface with a hydrofluoric acid (HF) containing cleaning solution; and carrying out a subsequent metal chemical mechanical polishing (CMP) process.

Abstract: A method for calibrating the wafer transfer system by using an inspection control wafer after plasma etching is described. An inspection control wafer is provided comprising a polysilicon layer overlying an oxide layer on the surface of a semiconductor substrate wherein the polysilicon layer does not cover the oxide layer for a first distance from the edge of the wafer. The inspection control wafer is entered into the wafer transfer system wherein the wafer is transferred to a spin-on-glass etchback chamber wherein the wafer is held by clamps which extend a second distance from the edge of the wafer and wherein there is designed an overlap difference between the first and second distances. The wafer is subjected to a spin-on-glass etchback step and then inspected for damage to the oxide layer. Oxide layer damage occurs if the second distance is less than the first distance by more than the overlap difference. Oxide layer damage indicates the need to recalibrate the wafer transfer system.

Abstract: A method for calibrating the wafer transfer system by using an inspection control wafer after plasma etching is described. An inspection control wafer is provided comprising a polysilicon layer overlying an oxide layer on the surface of a semiconductor substrate wherein the polysilicon layer does not cover the oxide layer for a first distance from the edge of the wafer. The inspection control wafer is entered into the wafer transfer system wherein the wafer is transferred to a spin-on-glass etchback chamber wherein the wafer is held by clamps which extend a second distance from the edge of the wafer and wherein there is designed an overlap difference between the first and second distances. The wafer is subjected to a spin-on-glass etchback step and then inspected for damage to the oxide layer. Oxide layer damage occurs if the second distance is less than the first distance by more than the overlap difference. Oxide layer damage indicates the need to recalibrate the wafer transfer system.

Abstract: A method for calibrating the wafer transfer system by using an inspection control wafer after plasma etching is described. An inspection control wafer is provided comprising a polysilicon layer overlying an oxide layer on the surface of a semiconductor substrate wherein the polysilicon layer does not cover the oxide layer for a first distance from the edge of the wafer. The inspection control wafer is entered into the wafer transfer system wherein the wafer is transferred to a spin-on-glass etchback chamber wherein the wafer is held by clamps which extend a second distance from the edge of the wafer and wherein there is designed an overlap difference between the first and second distances. The wafer is subjected to a spin-on-glass etchback step and then inspected for damage to the oxide layer. Oxide layer damage occurs if the second distance is less than the first distance by more than the overlap difference. Oxide layer damage indicates the need to recalibrate the wafer transfer system.

Abstract: A method for fabricating polycide gate electrodes wherein silicon pits in the active region are avoided by using a two-step etch to prevent pinholes in a BARC layer from penetrating significantly the silicide layer is described. A layer of gate silicon oxide is grown over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate silicon oxide layer. A silicide layer is formed overlying the polysilicon layer. A hard mask layer is deposited overlying the silicide layer. An anti-reflective coating layer is formed overlying the hard mask layer. A photoresist mask is formed over the anti-reflective coating layer wherein a pinhole is formed in the surface of the anti-reflective coating layer not covered by the photoresist mask. First the anti-reflective coating layer is etched through using O2 and N2 gases where it is not covered by the photoresist mask to the hard mask layer.

Abstract: A method for forming a patterned polysilicon layer within a microelectronics fabrication. There is first provided a substrate layer employed within a microelectronics fabrication. There is then formed upon the substrate layer a blanket polysilicon layer. There is then formed upon the blanket polysilicon layer a blanket organic polymer layer. There is then formed upon the blanket organic polymer layer a patterned photoresist layer, where the patterned photoresist layer has a high areal density region and a low areal density region. There is then etched through a first plasma etch method while employing the patterned photoresist layer as an etch mask layer the blanket organic polymer layer to form a patterned organic polymer layer while reaching the blanket polysilicon layer.

Abstract: A composite shadow ring for use in an etch chamber that does not generate contaminating oxygen gas when bombarded by a gas plasma and a method for using such composite shadow ring are presented. The composite shadow ring may have a structure of a body portion of a ring shape that is made of a material that is substantially of silicon dioxide and an insert portion which is intimately joined to the body portion and is adjacent to a plasma cloud in the etch chamber when the shadow ring is positioned juxtaposed to the wafer, the insert portion of the shadow ring may also have a ring shape and is eccentric with the body portion, it generally has a diameter smaller than a diameter of the body portion, the insert portion may be fabricated of a material that does not generate oxygen when bombarded by a fluorine-containing gas plasma. The body portion may have a crosssection of a rectangle which has an upper inner corner of the rectangle missing to form a cavity for receiving an insert member intimately therein.

Abstract: This invention describes a three-step process for etching a layer of silicon nitride over a thin layer of silicon dioxide on a semiconductor substrate for producing silicon nitride pattern with nearly vertical sidewalls, very small critical dimension bias and no trenching in the silicon dioxide, comprising a first step of a highly anisotropic etch process with a high etch rate, achieved by adding CHF.sub.3 to the gaseous mixture of SF.sub.6 and He, carried out at a relatively high power and low pressure, used to etch the bulk of the silicon nitride layer, a second step of lower etch anisotropy and etch rate, achieved by replacing CHF.sub.3 with HBr, carried out at higher pressure and lower power, used to etch out the remainder of the nitride layer with a small over-etch beyond the end point, a third step of high Si.sub.3 N.sub.4 /SiO.sub.2 etch selectivity, achieved by adding an oxidant to the reactive gas mixture, used to remove any remaining silicon nitride residues.