Patents by Inventor Yuh-Harng Chien

Yuh-Harng Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942448
    Abstract: An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive pad having a generally planar top surface that includes a cavity having a bottom surface and sidewalls extending from the bottom surface of the cavity to the top surface of the pad. An electronic device is attached to the top surface of the electrically conductive pad. A wire bond is attached from the electronic device to the bottom surface of the cavity. A molding compound encapsulates the electronic device.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bo-Hsun Pan, Hung-Yu Chou, Chung-Hao Lin, Yuh-Harng Chien
  • Patent number: 11862538
    Abstract: In some examples a semiconductor chip package includes a conductive terminal. In addition, the semiconductor chip package includes a die pad including a top side and a recess extending into the top side. The die pad is downset relative to the conductive terminal. Further, the semiconductor ship package includes a semiconductor die positioned within the recess, wherein the semiconductor die has an outer perimeter, and a solder fillet engaged within the recess and with the outer perimeter of the semiconductor die. Still further, the semiconductor chip package includes a wire bond coupled to the semiconductor die and the conductive terminal, and a mold compound covering the conductive terminal, the wire bond, the die pad, and the semiconductor die.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 2, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chung-Hao Lin, Hung-Yu Chou, Bo-Hsun Pan, Dong-Ren Peng, Pi-Chiang Huang, Yuh-Harng Chien
  • Publication number: 20230395472
    Abstract: In an example, an apparatus comprises a lead frame that includes a first row of leads, a first pad coupled to th first row of leads, and a second row of leads parallel to the first row of leads. The lead frame also includes a second pad coupled to the second row of leads. The first and second pads are separated by a gap, and each of the first and second pads has a substantially uniform thickness. The apparatus also includes a device coupled to the first and second pads. The first and second pads are exposed to an exterior of the apparatus.
    Type: Application
    Filed: August 22, 2023
    Publication date: December 7, 2023
    Inventors: Hung-Yu CHOU, Bo-Hsun PAN, Yuh-Harng CHIEN, Fu-Hua YU, Steven Alfred KUMMERL, Jie CHEN, Rajen M. MURUGAN
  • Patent number: 11817374
    Abstract: A packaged electronic device has a package structure, first leads, second leads and a tie bar. The package structure has a first side, a second side, a third side, a fourth side, a fifth side and a sixth side, the second side spaced from the first side along a first direction, the fourth side spaced from the third side along an orthogonal second direction, and the sixth side spaced from the fifth side along an orthogonal third direction. The first leads extend outward in a first plane of the second and third directions from respective portions of the third side, the second leads extend outward in the first plane from respective portions of the fourth side, and the tie bar is exposed along the fifth side in a second plane of the second and third directions, the second plane between the first plane and the first side.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: November 14, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Chih-Chien Ho, Bo-Hsun Pan, Yuh-Harng Chien
  • Publication number: 20230317571
    Abstract: An electronic device with a conductive lead having an internal first section and an external second section extending outside a molded package structure, the first section having an obstruction feature extending vertically from a top or bottom side of the conductive lead and engaging a portion of the package structure to oppose movement of the conductive lead outward from the package structure.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventors: Hsiang Ming Hsiao, Hung-Yu Chou, Yuh-Harng Chien, Chih-Chien Ho, Che Wei Tu, Bo-Hsun Pan, Megan Chang
  • Patent number: 11742265
    Abstract: In some examples, a semiconductor package comprises a lead frame. The lead frame includes a first row of leads; a first pad coupled to the first row of leads; a second row of leads; and a second pad coupled to the second row of leads, the first and second pads separated by a gap. The semiconductor package includes a heat-generating device coupled to the first and second pads and exposed to an exterior of the semiconductor package.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: August 29, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hung-Yu Chou, Chi-Chen Chien, Yuh-Harng Chien, Steven Alfred Kummerl, Bo-Hsun Pan, Fu-Hua Yu
  • Patent number: 11735506
    Abstract: In an example, an apparatus comprises a lead frame that includes a first row of leads, a first pad coupled to the first row of leads, and a second row of leads parallel to the first row of leads. The lead frame also includes a second pad coupled to the second row of leads. The first and second pads are separated by a gap, and each of the first and second pads has a substantially uniform thickness. The apparatus also includes a device coupled to the first and second pads. The first and second pads are exposed to an exterior of the apparatus.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 22, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hung-Yu Chou, Bo-Hsun Pan, Yuh-Harng Chien, Fu-Hua Yu, Steven Alfred Kummerl, Jie Chen, Rajen M. Murugan
  • Publication number: 20230063262
    Abstract: In some examples a semiconductor chip package includes a conductive terminal. In addition, the semiconductor chip package includes a die pad including a top side and a recess extending into the top side. The die pad is downset relative to the conductive terminal. Further, the semiconductor ship package includes a semiconductor die positioned within the recess, wherein the semiconductor die has an outer perimeter, and a solder fillet engaged within the recess and with the outer perimeter of the semiconductor die. Still further, the semiconductor chip package includes a wire bond coupled to the semiconductor die and the conductive terminal, and a mold compound covering the conductive terminal, the wire bond, the die pad, and the semiconductor die.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Chung-Hao LIN, Hung-Yu CHOU, Bo-Hsun PAN, Dong-Ren PENG, Pi-Chiang HUANG, Yuh-Harng CHIEN
  • Publication number: 20230016577
    Abstract: An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive pad having a generally planar top surface that includes a cavity having a bottom surface and sidewalls extending from the bottom surface of the cavity to the top surface of the pad. An electronic device is attached to the top surface of the electrically conductive pad. A wire bond is attached from the electronic device to the bottom surface of the cavity. A molding compound encapsulates the electronic device.
    Type: Application
    Filed: July 16, 2021
    Publication date: January 19, 2023
    Inventors: Bo-Hsun Pan, Hung-Yu Chou, Chung-Hao Lin, Yuh-Harng Chien
  • Patent number: 11538740
    Abstract: A semiconductor package includes a first lead with first and second ends extending in the same direction as one another. At least one second lead has first and second ends and is partially surrounded by the first lead. A die pad is provided and a die is connected to the die pad. Wires electrically connect the die to the first lead and the at least one second lead. An insulating layer extends over the leads, the die pad, and the die such that the first end of the at least one second lead is exposed from the semiconductor package and the second end of the first lead is encapsulated entirely within the insulating layer.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 27, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jason Chien, Yuh-Harng Chien, J K Ho
  • Publication number: 20220336331
    Abstract: A packaged electronic device has a package structure, first leads, second leads and a tie bar. The package structure has a first side, a second side, a third side, a fourth side, a fifth side and a sixth side, the second side spaced from the first side along a first direction, the fourth side spaced from the third side along an orthogonal second direction, and the sixth side spaced from the fifth side along an orthogonal third direction. The first leads extend outward in a first plane of the second and third directions from respective portions of the third side, the second leads extend outward in the first plane from respective portions of the fourth side, and the tie bar is exposed along the fifth side in a second plane of the second and third directions, the second plane between the first plane and the first side.
    Type: Application
    Filed: April 14, 2021
    Publication date: October 20, 2022
    Inventors: Chih-Chien Ho, Bo-Hsun Pan, Yuh-Harng Chien
  • Patent number: 11444012
    Abstract: In a described example, an apparatus includes a package substrate with a split die pad having a slot between a die mount portion and a wire bonding portion; a first end of the wire bonding portion coupled to the die mount portion at one end of the slot; a second end of the wire bonding portion coupled to a first lead on the package substrate. At least one semiconductor die is mounted on the die mount portion; a first end of a first wire bond is bonded to a first bond pad on the at least one semiconductor die; a second end of the first wire bond is bonded to the wire bonding portion; and mold compound covers the at least one semiconductor die, the die mount portion, the wire bonding portion, and fills the slot.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: September 13, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yuh-Harng Chien, Chang-Yen Ko, Chih-Chien Ho
  • Publication number: 20210375640
    Abstract: An integrated circuit package having a shunt resistor with at least one self-aligning member that protrudes from a first surface, and a lead frame with at least one self-aligning feature that is a cavity within which the at least one self-aligning member is located, and an integrated circuit located on the lead frame.
    Type: Application
    Filed: August 12, 2021
    Publication date: December 2, 2021
    Inventors: Yuh-Harng CHIEN, Hung-Yu CHOU, Fu-Kang LEE, Steven Alfred KUMMERL
  • Publication number: 20210305139
    Abstract: In a described example, an apparatus includes a package substrate with a split die pad having a slot between a die mount portion and a wire bonding portion; a first end of the wire bonding portion coupled to the die mount portion at one end of the slot; a second end of the wire bonding portion coupled to a first lead on the package substrate. At least one semiconductor die is mounted on the die mount portion; a first end of a first wire bond is bonded to a first bond pad on the at least one semiconductor die; a second end of the first wire bond is bonded to the wire bonding portion; and mold compound covers the at least one semiconductor die, the die mount portion, the wire bonding portion, and fills the slot.
    Type: Application
    Filed: March 26, 2020
    Publication date: September 30, 2021
    Inventors: Yuh-Harng Chien, Chang-Yen Ko, Chih-Chien Ho
  • Patent number: 11081428
    Abstract: An electronic device includes a package structure with opposite first and second sides spaced apart along a first direction, opposite third and fourth sides spaced apart along a second direction, opposite fifth and sixth sides spaced apart along a third direction, the first, second, and third directions being orthogonal to one another. A set of first leads extend outward from the first side along the first direction, a set of second leads extend outward from the second side along the first direction, and a thermal pad includes a first portion that extends along a portion of the fifth side, and a second portion that extends along a portion of the third side to facilitate cooling and visual solder inspection when soldered to a host printed circuit board.
    Type: Grant
    Filed: August 10, 2019
    Date of Patent: August 3, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Stanley Chou, Yuh-Harng Chien, Steven Alfred Kummerl, Bo-Hsun Pan, Pi-Chiang Huang, Frank Yu, Chih-Chien Ho
  • Patent number: 11081429
    Abstract: A packaged semiconductor device includes a leadframe including a finger pad(s) that is integrated, and spans a finger pad area including a width narrower than its length. A first portion of the finger pad area provides a die support area. A second portion of the finger pad area provides a wire bond area including first and second wire bond pads on a first and second side of the die support area. One of the wire bond pads further includes a lead terminal integrally connected. The IC die has a top side with bond pads and a back side having a non-electrically conductive die attach material attached to the die support area. Bond wires extend from the bond pads to the first and second wire bond pads. A mold compound encapsulates the packaged semiconductor device leaving exposed at least the lead terminal on a bottom side of the packaged semiconductor device.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: August 3, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jason Chien, J K Ho, Yuh-Harng Chien
  • Publication number: 20210118779
    Abstract: In some examples, a semiconductor package comprises a lead frame. The lead frame includes a first row of leads; a first pad coupled to the first row of leads; a second row of leads; and a second pad coupled to the second row of leads, the first and second pads separated by a gap. The semiconductor package includes a heat-generating device coupled to the first and second pads and exposed to an exterior of the semiconductor package.
    Type: Application
    Filed: October 22, 2019
    Publication date: April 22, 2021
    Inventors: Hung-Yu CHOU, Chi-Chen CHIEN, Yuh-Harng CHIEN, Steven Alfred KUMMERL, Bo-Hsun PAN, Fu-Hua YU
  • Publication number: 20210111103
    Abstract: A packaged semiconductor device includes a leadframe including a finger pad(s) that is integrated, and spans a finger pad area including a width narrower than its length. A first portion of the finger pad area provides a die support area. A second portion of the finger pad area provides a wire bond area including first and second wire bond pads on a first and second side of the die support area. One of the wire bond pads further includes a lead terminal integrally connected. The IC die has a top side with bond pads and a back side having a non-electrically conductive die attach material attached to the die support area. Bond wires extend from the bond pads to the first and second wire bond pads. A mold compound encapsulates the packaged semiconductor device leaving exposed at least the lead terminal on a bottom side of the packaged semiconductor device.
    Type: Application
    Filed: October 14, 2019
    Publication date: April 15, 2021
    Inventors: Jason Chien, J K Ho, Yuh-Harng Chien
  • Patent number: 10957631
    Abstract: A leadframe comprising a plurality of leads, each of the plurality of leads having a proximal end and a distal end opposite the proximal end, the distal ends positioned along a linear axis. The leadframe further comprises a die pad closer to the proximal ends than the distal ends of the plurality of leads and including an edge positioned along a plane that intersects the linear axis at an angle less than 90 degrees.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: March 23, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Chung-Ming Cheng, Yuh-Harng Chien, Fu-Kang Lee, Chia-Yu Chang
  • Publication number: 20210043548
    Abstract: An electronic device includes a package structure with opposite first and second sides spaced apart along a first direction, opposite third and fourth sides spaced apart along a second direction, opposite fifth and sixth sides spaced apart along a third direction, the first, second, and third directions being orthogonal to one another. A set of first leads extend outward from the first side along the first direction, a set of second leads extend outward from the second side along the first direction, and a thermal pad includes a first portion that extends along a portion of the fifth side, and a second portion that extends along a portion of the third side to facilitate cooling and visual solder inspection when soldered to a host printed circuit board.
    Type: Application
    Filed: August 10, 2019
    Publication date: February 11, 2021
    Applicant: Texas Instruments Incorporated
    Inventors: Stanley Chou, Yuh-Harng Chien, Steven Alfred Kummerl, Bo-Hsun Pan, Pi-Chiang Huang, Frank Yu, Chih-Chien Ho