Abstract: A display panel includes a substrate, a display area, N data lines, first switches, second switches, third switches, and fourth switches. A first peripheral circuit zone, a second peripheral circuit zone, and a display area are defined on a first surface of the substrate, and located between the first peripheral circuit zone and the second peripheral circuit zone. A display area circuit is located in the display area. Each of the N data lines crosses the display area circuit from the first peripheral circuit zone to the second peripheral circuit zone, and N is a positive integer greater than 1. The first switches are located in the first peripheral circuit zone. The second switches are located in the first peripheral circuit zone. The third switches are located on the first surface. The fourth switches are located in the second peripheral circuit zone.

Abstract: A display panel includes a substrate, a display area, N data lines, first switches, second switches, third switches, and fourth switches. A first peripheral circuit zone, a second peripheral circuit zone, and a display area are defined on a first surface of the substrate, and located between the first peripheral circuit zone and the second peripheral circuit zone. A display area circuit is located in the display area. Each of the N data lines crosses the display area circuit from the first peripheral circuit zone to the second peripheral circuit zone, and N is a positive integer greater than 1. The first switches are located in the first peripheral circuit zone. The second switches are located in the first peripheral circuit zone. The third switches are located on the first surface. The fourth switches are located in the second peripheral circuit zone.

Abstract: A test cell structure of a display panel is disposed in the peripheral region of the display panel. First conductive lines and second conductive lines extend from the display region to the peripheral region, and the amounts of the first and second conductive lines are the same. The test cell structure includes a plurality of first test transistors, a plurality of second test transistors, and a plurality of first shorting bars. The drains of the first test transistors are electrically connected to the first conductive lines respectively, and their sources are electrically connected to the first shorting bars. The sources of the second test transistors are electrically connected to the drains of the first test transistors respectively, and their drains are electrically connected to the second conductive lines. The first test transistors are disposed between the second test transistors and the display region.

Abstract: A test cell structure of a display panel is disposed in the peripheral region of the display panel. First conductive lines and second conductive lines extend from the display region to the peripheral region, and the amounts of the first and second conductive lines are the same. The test cell structure includes a plurality of first test transistors, a plurality of second test transistors, and a plurality of first shorting bars. The drains of the first test transistors are electrically connected to the first conductive lines respectively, and their sources are electrically connected to the first shorting bars. The sources of the second test transistors are electrically connected to the drains of the first test transistors respectively, and their drains are electrically connected to the second conductive lines. The first test transistors are disposed between the second test transistors and the display region.

Abstract: A pixel structure of a color filtering array substrate includes a color filtering layer, a black matrix layer, and an electrode layer. The black matrix layer surrounds the color filtering layer. The electrode layer covers the color filtering layer and the black matrix layer. Besides, the electrode layer has at least one opening therein, and the opening is located above the black matrix layer.

Abstract: A pixel structure of an active device array substrate is provided. The pixel structure includes a scan line and a data line; an active device electrically coupled to the scan line and the data line; a pixel electrode electrically coupled to the active device, wherein the pixel electrode has at least one opening therein; and at least one island electrode disposed inside the opening, wherein the island electrode is electrically coupled to a voltage V, and the pixel electrode is electrically coupled to a driving voltage Vd that is different from the voltage V, such that a transverse electric field is formed between the island electrode and the pixel electrode.

Abstract: A pixel structure of a color filtering array substrate includes a color filtering layer, a black matrix layer, and an electrode layer. The black matrix layer surrounds the color filtering layer. The electrode layer covers the color filtering layer and the black matrix layer. Besides, the electrode layer has at least one opening therein, and the opening is located above the black matrix layer.

Abstract: A pixel structure of an active device array substrate is provided. The pixel structure includes a scan line and a data line; an active device electrically coupled to the scan line and the data line; a pixel electrode electrically coupled to the active device, wherein the pixel electrode has at least one opening therein; and at least one island electrode disposed inside the opening, wherein the island electrode is electrically coupled to a voltage V, and the pixel electrode is electrically coupled to a driving voltage Vd that is different from the voltage V, such that a transverse electric field is formed between the island electrode and the pixel electrode.