Abstract: A method and structure for preventing film delamination provide for forming a thick film then partitioning the thick film into a plurality of discrete portions prior to subsequent thermal processing operations. The partitioning alleviates the effects of film stress at the interface between the film and the underlying material and prevents delamination during the subsequent thermal cycling operations, that take place subsequent to the formation of the film. The partitioned film includes a pattern density of at least about 80 percent and the discrete portions do not individually serve as device structures.

Abstract: An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.

Abstract: A method of planarizing a dielectric insulating layer including providing a substrate including forming a first dielectric insulating layer having a concave and convex portion on the substrate; forming an organic resinous layer on the first dielectric insulating layer and exposing the convex portion of the first dielectric insulating layer; isotropically etching the first dielectric insulating layer convex portion; removing the organic resinous layer; and, forming a second dielectric insulating layer on the first dielectric insulating layer.

Abstract: An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.

Abstract: A method for forming a MEMS device using an amorphous silicon layer as a release layer includes etching superjacent films and using the amorphous silicon layer as an etch stop layer. The amorphous silicon layer is resistant to attack during the post-etch solvent stripping operation due to the oxidation of exposed portions of the amorphous silicon layer by use of an oxygen plasma.

Abstract: A method and structure for preventing film delamination provide for forming a thick film then partitioning the thick film into a plurality of discrete portions prior to subsequent thermal processing operations. The partitioning alleviates the effects of film stress at the interface between the film and the underlying material and prevents delamination during the subsequent thermal cycling operations, that take place subsequent to the formation of the film. The partitioned film includes a pattern density of at least about 80 percent and the discrete portions do not individually serve as device structures.

Abstract: A method of planarizing a dielectric insulating layer including providing a substrate including forming a first dielectric insulating layer having a concave and convex portion on the substrate; forming an organic resinous layer on the first dielectric insulating layer and exposing the convex portion of the first dielectric insulating layer; isotropically etching the first dielectric insulating layer convex portion; removing the organic resinous layer; and, forming a second dielectric insulating layer on the first dielectric insulating layer.

Abstract: An MEMS mirror structure is formed using an etching process that forms sidewall oxide spacers while maintaining the integrity of the oxide layer formed over the reflective layer of the MEMS mirror structure. The discrete mirror structure is formed to include a reflective layer sandwiched between oxide layers and with a protect layer formed over the upper oxide layer. A spacer oxide layer is formed to cover the structure and oxide spacers are formed on sidewalls of the discrete structure using a selective etch process that is terminated when horizontal portions of the spacer oxide layer have cleared to expose the release layer formed below the discrete mirror structure and the protect layer. The superjacent protect layer prevents the spacer oxide etch process from attacking the upper oxide layer and therefore maintains the integrity of the upper oxide layer and the functionality of the mirror structure.

Abstract: A transparent substrate has a micro electro-mechanical system (MEMS) on a first side of the substrate. An opaque layer is formed on a second side of the transparent substrate opposite the first side. The opaque layer comprises a first material that is removable by a MEMS release process. A second layer is formed on the opaque layer. The second layer comprises a second material that prevents contamination of a front end of line machine by the first material during a front end of line fabrication process.

Abstract: A product comprising a micromirror comprising a reflective layer and a treatment layer overlying the reflective layer, and wherein the treatment layer comprises Ti.

Abstract: A transparent substrate has a micro electromechanical system (MEMS) on a first side of the substrate. An opaque layer is formed on a second side of the transparent substrate opposite the first side. The opaque layer comprises a first material that is removable by a MEMS release process. A second layer is formed on the opaque layer. The second layer comprises a second material that prevents contamination of a front end of line machine by the first material during a front end of line fabrication process.

Abstract: A method for forming a MEMS device using an amorphous silicon layer as a release layer includes etching superjacent films and using the amorphous silicon layer as an etch stop layer. The amorphous silicon layer is resistant to attack during the post-etch solvent stripping operation due to the oxidation of exposed portions of the amorphous silicon layer by use of an oxygen plasma.

Abstract: A micromirror which includes a substrate, a reflective layer comprising pure aluminum overlying the substrate and a protective layer comprising titanium nitride overlying the reflective layer is disclosed.

Abstract: The disclosure relates to a method and apparatus for preventing extrusion or spiking of a metal atom from a metallization layer to other layers of a silicon wafer. In one embodiment, the method includes forming a silicon-on-ship device with a MEMS component on the substrate. The MEMS component may include one or more metal or metallic alloys. To prevent spiking from the MEMS component, the sides thereof can be coated with one ore more spacer or barrier layers. In one embodiment, oxygen plasma and thermal oxidation methods are used to deposit spacers. In another embodiment, an oxide layer is deposited over the wafer, covering the substrate and the MEMS component. Selective etching or anisotropic etching can be used to remove the oxide layer from certain regions of the MEMS and the substrate while covering the sidewalls. An amorphous silicon layer can then be deposited to cover the MEMS device.

Abstract: A system and method for forming a split-gate flash memory cell is disclosed. In one example, a method for forming a semiconductor device includes: supplying a substrate; forming a floating gate with alternate etch and passivation steps; and forming a control gate proximate to and partially overlying the floating gate.

Abstract: A micromirror which includes a substrate, a reflective layer comprising pure aluminum overlying the substrate and a protective layer comprising titanium nitride overlying the reflective layer is disclosed.

Abstract: An MEMS mirror structure is formed using an etching process that forms sidewall oxide spacers while maintaining the integrity of the oxide layer formed over the reflective layer of the MEMS mirror structure. The discrete mirror structure is formed to include a reflective layer sandwiched between oxide layers and with a protect layer formed over the upper oxide layer. A spacer oxide layer is formed to cover the structure and oxide spacers are formed on sidewalls of the discrete structure using a selective etch process that is terminated when horizontal portions of the spacer oxide layer have cleared to expose the release layer formed below the discrete mirror structure and the protect layer. The superjacent protect layer prevents the spacer oxide etch process from attacking the upper oxide layer and therefore maintains the integrity of the upper oxide layer and the functionality of the mirror structure.

Abstract: A new method is provided for monitoring the effect of electron charging during the creation of a semiconductor device. The method of the invention makes use of electron trapping that occurs as a result of FN tunneling in a layer of interlayer oxide of an EEPROM device. The electron trapping is monitored under conditions of processing. After the electron trapping has occurred, the rate of discharge of the trapped electron charge is measured during Wafer Acceptance Testing (WAT).

Abstract: A double substrate spatial light modulator with an enlarged tilt angle is achieved. The device comprises a mirror attached on one end to a hinge wherein the hinge is attached to support posts adjacent to the mirror and attached to an underlying glass substrate, a trench within the glass substrate adjacent to the support posts wherein the mirror tilts upward from the glass substrate and downward into the trench, and an overlying glass substrate. The trench provides an enlarged tilt angle of mirror motion. This improves optical performance of the mirror projector including contrast ratio and gray scale.

Abstract: A method of fabricating a double substrate spatial light modulator wherein the mirror sidewall residue problem is eliminated is described. A first sacrificial layer is formed overlying a glass substrate. A metal layer is deposited overlying the first sacrificial layer. First openings are formed in the metal layer. A second sacrificial layer is formed overlying the metal layer and within the first openings. The second sacrificial layer is patterned to form hinge openings to the metal layer and the second and first sacrificial layers are patterned to form post openings to the substrate within the first openings. Support posts are formed within the post openings and hinges are formed within the hinge openings wherein each of the hinges is connected to the support posts on either side of the hinge openings. Thereafter, the metal layer is patterned to form a plurality of micromirrors wherein each of the plurality of micromirrors is attached on one end to one of the hinges through the hinge openings.