Abstract: A method for a base station (BS) instructing a UE to monitor a physical downlink control channel (PDCCH) for power saving signaling is disclosed. The method comprises transmitting a discontinuous reception (DRX) configuration to the UE indicating to monitor a scheduling signal on the PDCCH within a DRX active time, and transmitting a configuration to the UE for monitoring the power saving signaling on the PDCCH, instructing the UE to wake up for monitoring the scheduling signal in the DRX active time, wherein the configuration includes a time in milliseconds prior to a start of a DRX on-duration time, and instructs the UE to start monitoring the PDCCH for the power saving signaling.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The substrate has a base and a multilayer structure over the base, and the gate stack wraps around the multilayer structure. The method includes partially removing the multilayer structure, which is not covered by the gate stack. The multilayer structure remaining under the gate stack forms a multilayer stack, and the multilayer stack includes a sacrificial layer and a channel layer over the sacrificial layer. The method includes partially removing the sacrificial layer to form a recess in the multilayer stack. The method includes forming an inner spacer layer in the recess and a bottom spacer over a sidewall of the channel layer. The method includes forming a source/drain structure over the bottom spacer. The bottom spacer separates the source/drain structure from the channel layer.

Abstract: Described herein are—inter alia—complexes comprising a curcuminoid; and an anionic surfactant. Methods of making and using same are also described.

Abstract: A method for manufacturing a part-embedded circuit structure includes: forming an inner resist layer with an opening on a base member to expose a portion of the base member; forming an inner wiring layer on the inner resist layer which extends into the opening of the inner resist layer; laminating a dielectric layer on the inner wiring layer; forming an outer wiring layer on the dielectric layer opposite to the inner wiring layer; and removing the base member to expose the inner wiring layer in the opening and the inner resist layer such that a level plane is formed.