Abstract: This application relates to a novel chlorhexidine lauryl sulfate salt, which provides enhanced chlorhexidine stability and enhanced anti-bacterial activity, and to formulations and methods utilizing the novel salt.

Abstract: A semiconductor structure includes a substrate, a first gate structure and a second gate structure disposed over the substrate, and an isolation feature extending through the substrate and disposed between the first gate structure and the second gate structure. A top surface of the isolation feature is above a topmost surface of the first gate structure.

Abstract: A method for a user equipment (UE) monitoring a physical downlink control channel (PDCCH) for power saving signaling is disclosed. The method comprises receiving a discontinuous reception (DRX) configuration from a base station (BS) to configure the UE to monitor a scheduling signal on the PDCCH within a DRX active time, and receiving a configuration from the BS to configure the UE to monitor the power saving signaling on the PDCCH and instructing the UE to wake up for monitoring the scheduling signal in the DRX active time, wherein the configuration includes a time in milliseconds prior to a start of a DRX on-duration time, and instructs the UE to start monitoring the PDCCH for the power saving signaling.

Abstract: A device for treating a user's skin using plasma is provided. The device comprises a plasma generation assembly and a power supply. The plasma generation assembly comprises a discharge electrode including a first surface; a first dielectric material layer provided on the first surface of the discharge electrode and the first surface, a ground electrode surrounding the discharge electrode, and an insulation member spacing around the discharge electrode from the ground electrode. The power supply configured to apply power to the plasma generation assembly so that plasma is generated from the first surface of the discharge electrode to the ground electrode and between the first dielectric material layer and the user's skin.

Abstract: An intraocular pressure inspection device includes an intraocular pressure detection unit, a high-precision positioning system and a wide-area positioning system, wherein according to the position of the intraocular pressure detection unit, a set of high-precision coordinates output by the high-precision positioning system and a set of wide-area coordinates output by the wide-area positioning system are integrated in appropriate weights to obtain a set of more precise integrated coordinate. The above-mentioned intraocular pressure inspection device can prevent the intraocular pressure detection unit from failing to operate once it is not in the working area of the high-precision positioning system.

Abstract: A probe card, a method for designing the probe card, a method for producing a tested semiconductor device, a method for testing an unpackaged semiconductor by the probe card, a device under test, and a probe system are provided. The probe card includes a wiring substrate, a connection carrier board, and a probe device. At least two probes form a differential pair electrically connected to a loopback line of the connection carrier board to form a test signal loopback path. The probe device has a probe device impedance on the test signal loopback path. The loopback line has a loopback line impedance on the test signal loopback path. A difference between the probe device impedance on the test signal loopback path and the loopback line impedance on the test signal loopback path is in an impedance range.

Abstract: A package includes a first package component including a semiconductor die, wherein the semiconductor die includes conductive pads, wherein the semiconductor die is surrounded by an encapsulant; an adaptive interconnect structure on the semiconductor die, wherein the adaptive interconnect structure includes conductive lines, wherein each conductive line physically and electrically contacts a respective conductive pad; and first bond pads, wherein each first bond pad physically and electrically contacts a respective conductive line; and a second package component including an interconnect structure, wherein the interconnect structure includes second bond pads, wherein each second bond pad is directly bonded to a respective first bond pad, wherein each second bond pad is laterally offset from a corresponding conductive pad which is electrically coupled to that second bond pad.

Abstract: A method for manufacturing a part-embedded circuit structure includes: forming an inner resist layer with an opening on a base member to expose a portion of the base member; forming an inner wiring layer on the inner resist layer which extends into the opening of the inner resist layer; laminating a dielectric layer on the inner wiring layer; forming an outer wiring layer on the dielectric layer opposite to the inner wiring layer; and removing the base member to expose the inner wiring layer in the opening and the inner resist layer such that a level plane is formed.