Patents by Inventor YU-HAO CHENG

YU-HAO CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12243780
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The substrate has a base and a multilayer structure over the base, and the gate stack wraps around the multilayer structure. The method includes partially removing the multilayer structure, which is not covered by the gate stack. The multilayer structure remaining under the gate stack forms a multilayer stack, and the multilayer stack includes a sacrificial layer and a channel layer over the sacrificial layer. The method includes partially removing the sacrificial layer to form a recess in the multilayer stack. The method includes forming an inner spacer layer in the recess and a bottom spacer over a sidewall of the channel layer. The method includes forming a source/drain structure over the bottom spacer. The bottom spacer separates the source/drain structure from the channel layer.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Wei Tsai, Yu-Xuan Huang, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao, Jung-Hung Chang, Lo-Heng Chang, Pei-Hsun Wang, Kuo-Cheng Chiang
  • Publication number: 20250064697
    Abstract: Described herein are—inter alia—complexes comprising a curcuminoid; and an anionic surfactant. Methods of making and using same are also described.
    Type: Application
    Filed: November 13, 2024
    Publication date: February 27, 2025
    Applicant: Colgate-Palmolive Company
    Inventors: Payal ARORA, Harsh Mahendra TRIVEDI, Zhigang HAO, Paul THOMSON, Manish MANDHARE, Yu WANG, Chi-Yuan CHENG, Long PAN
  • Publication number: 20160066418
    Abstract: A method for manufacturing a part-embedded circuit structure includes: forming an inner resist layer with an opening on a base member to expose a portion of the base member; forming an inner wiring layer on the inner resist layer which extends into the opening of the inner resist layer; laminating a dielectric layer on the inner wiring layer; forming an outer wiring layer on the dielectric layer opposite to the inner wiring layer; and removing the base member to expose the inner wiring layer in the opening and the inner resist layer such that a level plane is formed.
    Type: Application
    Filed: September 1, 2015
    Publication date: March 3, 2016
    Inventors: YU-HAO CHENG, YUE WANG, WEN-HUNG HU