Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.

Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.

Abstract: A semiconductor structure includes a semiconductor epitaxial layer, a first semiconductor well, a second semiconductor well, a source doped region, a gate structure and a drain structure. The semiconductor epitaxial layer includes a first side and a second side opposite to the first side. The first semiconductor well is located on the first side of the semiconductor epitaxial layer. The second semiconductor well is located on the second side of the semiconductor epitaxial layer. The source doped region is located in the first semiconductor well. The gate structure overlaps the first semiconductor well and the source doped region on the first side of the semiconductor epitaxial layer. The drain structure includes a semiconductor substrate. The second side of the semiconductor epitaxial layer outside the second semiconductor well includes a connecting surface. The connecting surface of the semiconductor epitaxial layer is connected to the semiconductor substrate.

Abstract: A method of forming a semiconductor structure includes the following operations. A semiconductor epitaxial layer is formed on a first semiconductor substrate. A first side of the semiconductor epitaxial layer is adhered to a transfer substrate by an adhesive layer covering the first side of the semiconductor epitaxial layer. The semiconductor epitaxial layer and the first semiconductor substrate are turned over by the transfer substrate. The first semiconductor substrate is removed to expose a second side of the semiconductor epitaxial layer opposite to the first side. A first semiconductor doped region is formed on the second side of the semiconductor epitaxial layer. After the first semiconductor doped region is formed, the adhesive layer and the transfer substrate are removed.

Abstract: A method of wireless signal transmission management includes transmitting a plurality of data packets to tethering equipment from user equipment to tethering equipment, determining a size of each of the plurality of data packets by the tethering equipment, designating data packets of the plurality of data packets having a specific range of sizes as control signal packets by the tethering equipment, and prioritizing in transmitting the control signal packets to a cellular network by the tethering equipment.

Abstract: An apparatus includes a six-axis correction stage, an auto-collimation measurement device, a light splitter, a telecentric image measurement device, and a controller. The six-axis correction stage carries a device under test; the auto-collimation measurement device is arranged above the six-axis correction stage along a measurement optical axis; the light splitter is arranged on the measurement optical axis and is interposed between the six-axis correction stage and the auto-collimation measurement device. A method controls the six-axis correction stage to correct rotation errors in at least two degrees of freedom of the device under test according to a measurement result of the auto-collimation measurement device, and controls the six-axis correction stage to correct translation and yaw errors in at least three degrees of freedom of the device under test according to a measurement result of the telecentric image measurement device by means of the controller.

Abstract: In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

Abstract: Some embodiments relate to an integrated chip including a plurality of conductive structures over a substrate. A first dielectric layer is disposed laterally between the conductive structures. A spacer structure is disposed between the first dielectric layer and the plurality of conductive structures. An etch stop layer overlies the plurality of conductive structures. The etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.

Abstract: The present invention relates to an organic light emitting diode, comprising: a first electrode; an organic material layer which comprises a hole transport layer, an electron transport layer and an light emitting layer, wherein the hole transport layer may be interposed between the first electrode and the light emitting layer, and the light emitting layer may be interposed between the hole transport layer and the electron transport layer; a second electrode which is disposed on the organic material layer; and a carrier conversion layer which may be interposed between the first electrode and the hole transport layer or between the second electrode and the electron transport layer; wherein the carrier conversion layer has a thickness of 10 nm to 200 nm.

Abstract: An organic light emitting diode (OLED) display is provided. The OLED display includes a first electrode layer, a second electrode layer, a first light emitting layer, a second light emitting layer, a first n-type charge generation layer, a second n-type charge generation layer, and a metal layer. The first light emitting layer and the second light emitting layer are formed between the first electrode layer and the second electrode layer. The first n-type charge generation layer and the second n-type charge generation layer are formed between the first light emitting layer and the second light emitting layer. The metal layer is formed between the first n-type charge generation layer and the second n-type charge generation layer, wherein the metal layer has a first thickness.

Abstract: An organic light-emitting diode (OLED) display panel is provided. The OLED display panel includes a pixel. The pixel includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first light emitting unit and a second light emitting unit. The first light emitting unit is used for emitting a first color light. The second light emitting unit is used for emitting a second color light. The second sub-pixel includes a third light emitting unit and a fourth light emitting unit. The third light emitting unit is used for emitting a third color light. The fourth light emitting unit is used for emitting a fourth color light. The combination of the first color light and the second color light is different from the combination of the third color light and the fourth color light.

Abstract: The present invention relates to an organic light emitting diode, comprising: a first electrode; an organic material layer which comprises a hole transport layer, an electron transport layer and an light emitting layer, wherein the hole transport layer may be interposed between the first electrode and the light emitting layer, and the light emitting layer may be interposed between the hole transport layer and the electron transport layer; a second electrode which is disposed on the organic material layer; and a carrier conversion layer which may be interposed between the first electrode and the hole transport layer or between the second electrode and the electron transport layer; wherein the carrier conversion layer has a thickness of 10 nm to 200 nm.

Abstract: Disclosed is a method for making a bit of a tool. The method includes the steps of providing a blank, forging, cutting and pressing. The size of the blank is determined according to the size of the bit. By the forging, the blank is made with a connective section and a neck. The connective section is formed with a polygonal profile, a first chamfer at an end thereof and a second chamfer at another end thereof. The neck extends from the polygonal connective section and includes ribs separated from one another by grooves. By the cutting, the neck is made with a tapered section. By the pressing, the tapered section of the neck is turned into a driving section of the bit to reduce the length of the tapered section of the neck but increase the width of the tapered section of the blank.

Abstract: An apparatus is disclosed for making aligned inclined holes in upper and lower work piece. The apparatus includes a set of drill bits and an alignment element. Each of the drill bits can be driven into the upper and lower work pieces to make the inclined holes. The alignment element includes a horizontal plate, a vertical plate extended from the horizontal plate and a tube extended from a corner formed between the horizontal and vertical plates. The horizontal plate is used for contact with the upper work piece. The vertical plate is used for contact with the lower work piece. The tube includes a tunnel for receiving a selected one of the drill bits, a space for receiving debris produced because of the drilling and an aperture through which the selected drill bit is inserted into the space from the tunnel.

Abstract: A screwdriver includes a shank and a head formed at an end of the shank. The shank is made with a diameter. The head is formed with blades. Each of the blades includes an edge. The distance between the edges of any two opposite ones of the blades is larger than the diameter of the shank.

Abstract: A floatable hand tool includes a shank having an inner wall formed with an axially extending through hole, and a tool tip mounted on an end of the shank and having an end portion provided with a protruding connecting rod inserted into the through hole of the shank so that the through hole of the shank forms a closed chamber. Thus, the floatable hand tool floats on the water level by the floating force produced by the closed chamber the through hole of the shank. In addition, the floatable hand tool floats on the water level, thereby preventing the floatable hand tool from being missed when falling into the water, and thereby facilitating a user operating the floatable hand tool in the water.