Abstract: An active matrix substrate includes a first TFT disposed in each of pixel regions, a first flattened layer covering the first TFT, and a pixel electrode provided on the first flattened layer. The first TFT includes a lower gate electrode, a lower gate insulating layer, an oxide semiconductor layer, an upper gate insulating layer, and an upper gate electrode. The active matrix substrate further includes a first connection electrode for electrically connecting a drain contact region of the oxide semiconductor layer and the pixel electrode. The first flattened layer includes a pixel contact hole formed so as to expose a part of the first connection electrode. The bottom face of the pixel contact hole at least partially overlaps, of a lower gate metal layer including a lower gate electrode and an upper gate metal layer including an upper gate electrode, at least the lower gate metal layer when viewed from the normal direction of the substrate.

Abstract: One conductor region of a crystalline silicon semiconductor layer in a first transistor is electrically connected to one conductor region of an oxide semiconductor layer in a second transistor through a first contact hole and a second contact hole communicating with each other.

Abstract: An active matrix substrate includes: a thin film transistor located in each pixel region; and a pixel electrode electrically coupled with the thin film transistor. The thin film transistor includes a lower gate electrode, a lower gate insulating layer, an oxide semiconductor layer, an upper gate insulating layer, and an upper gate electrode. The width of an upper gate line electrically coupled with the upper gate electrode is greater than the width of a lower gate line electrically coupled with the lower gate electrode.

Abstract: A display device includes a pixel circuit and a light-emitting element, the pixel circuit including: a transistor with a first structure including a crystalline silicon semiconductor film and a first gate electrode; and a transistor with a second structure including an oxide semiconductor film and a second gate electrode, the display device further includes: a first interlayer insulation film; and a second interlayer insulation film, wherein the pixel circuit includes: a drive transistor that has the first structure: and a capacitive element, the capacitive element includes: a first capacitor electrode electrically connected to a first gate electrode of the drive transistor; a second capacitor electrode opposite the first capacitor electrode; and a dielectric film between the first capacitor electrode and the second capacitor electrode, and the dielectric film is disposed in a different layer than are the first interlayer insulation film and the second interlayer insulation film.

Abstract: An active matrix substrate includes a substrate, a pixel TFT that is supported by the substrate, provided corresponding to each of a plurality of pixel areas, and includes an oxide semiconductor layer, an organic insulating layer disposed above at least the oxide semiconductor layer of the pixel TFT, and an inorganic insulating layer disposed in contact with an upper surface of the organic insulating layer on the organic insulating layer. The organic insulating layer and the inorganic insulating layer are provided with a plurality of dual-layer hole structure portions, each of the dual-layer hole structure portions includes a through-hole provided in the inorganic insulating layer and a bottomed hole provided in the organic insulating layer and positioned below the through-hole, and the through-hole is positioned on an inner side of an outer edge of the bottomed hole when viewed from a normal direction of the substrate.

Abstract: An active matrix substrate includes a first TFT disposed in each of pixel regions, a first flattened layer covering the first TFT, and a pixel electrode provided on the first flattened layer. The first TFT includes a lower gate electrode, a lower gate insulating layer, an oxide semiconductor layer, an upper gate insulating layer, and an upper gate electrode. The active matrix substrate further includes a first connection electrode for electrically connecting a drain contact region of the oxide semiconductor layer and the pixel electrode. The first flattened layer includes a pixel contact hole formed so as to expose a part of the first connection electrode. The bottom face of the pixel contact hole at least partially overlaps, of a lower gate metal layer including a lower gate electrode and an upper gate metal layer including an upper gate electrode, at least the lower gate metal layer when viewed from the normal direction of the substrate.

Abstract: An oxide semiconductor layer includes a second channel region and a second conductor region. The lower metal layer includes a contact wire in contact with the second conductor region. The upper metal layer includes an upper wire. A second interlayer insulating film is provided with a second contact hole overlapping an upper wire and the contact wire. The second conductor region and the upper wire electrically connect together through the contact wire.

Abstract: A crystalline silicon semiconductor layer includes a first channel region and a second conductor region. An oxide semiconductor layer includes a second channel region and a second conductor region. An lower metal layer includes a lower wire. The lower wire is in contact with a first conductor region in a first contact hole. The first conductor region and the second conductor region are electrically connected together through the lower wire.

Abstract: One conductor region of a crystalline silicon semiconductor layer in a first transistor is electrically connected to one conductor region of an oxide semiconductor layer in a second transistor through a first contact hole and a second contact hole communicating with each other.

Abstract: Provided is a method for manufacturing a semiconductor device, the semiconductor device including a substrate, and an oxide semiconductor TFT that is supported by the substrate and includes an oxide semiconductor film as an active layer. The method includes: (A) preparing MO gas containing a first organometallic compound that contains In and a second organometallic compound that contains Zn; and (B) supplying gas containing the MO gas and oxygen to the substrate placed in a chamber under a condition in which the substrate is heated to 500° C. or lower, and growing an oxide semiconductor film containing In and Zn on the substrate using an MOCVD method. Step (B) is performed under a condition in which plasma is formed in the chamber.

Abstract: An active matrix substrate according to an aspect of the disclosure includes a pixel portion including a plurality of gate lines and a plurality of source lines, and a plurality of pixel electrodes, and a split switch circuit configured to split a signal from a source driver to supply to the plurality of source lines, wherein the pixel portion includes a first TFT including a first oxide semiconductor layer, the split switch circuit includes a second TFT including a second oxide semiconductor layer and a third oxide semiconductor layer, and the third oxide semiconductor layer covers at least a portion of an upper face and a portion of an edge face of the second oxide semiconductor layer.

Abstract: An active matrix substrate includes a demultiplexer circuit which includes multiple TFTs. Each TFT includes a gate electrode, an oxide semiconductor layer that includes a source contact area, a drain contact area, and an area between a source and a drain that includes a channel region, a channel protection layer that covers only a portion of the area between the source and the drain, a source electrode that is brought into contact with the source contact area, and a drain electrode that is brought into contact with the drain contact area. At a cross-section in a channel length direction, of each TFT, an end portion facing toward the channel region, of one of the source and drain electrodes is brought into contact with the channel protection layer, and an end portion facing toward the channel region, of the other is positioned at a distance away from the channel protection layer.

Abstract: Provided is a method for manufacturing a semiconductor device, the semiconductor device including a substrate, and an oxide semiconductor TFT that is supported by the substrate and includes an oxide semiconductor film as an active layer. The method includes: (A) preparing MO gas containing a first organometallic compound that contains In and a second organometallic compound that contains Zn; and (B) supplying gas containing the MO gas and oxygen to the substrate placed in a chamber under a condition in which the substrate is heated to 500° C. or lower, and growing an oxide semiconductor film containing In and Zn on the substrate using an MOCVD method. Step (B) is performed under a condition in which plasma is formed in the chamber.

Abstract: An active matrix substrate according to an aspect of the disclosure includes a pixel portion including a plurality of gate lines and a plurality of source lines, and a plurality of pixel electrodes, and a split switch circuit configured to split a signal from a source driver to supply to the plurality of source lines, wherein the pixel portion includes a first TFT including a first oxide semiconductor layer, the split switch circuit includes a second TFT including a second oxide semiconductor layer and a third oxide semiconductor layer, and the third oxide semiconductor layer covers at least a portion of an upper face and a portion of an edge face of the second oxide semiconductor layer.

Abstract: An active matrix substrate includes a demultiplexer circuit which includes multiple TFTs. Each TFT includes a gate electrode, an oxide semiconductor layer that includes a source contact area, a drain contact area, and an area between a source and a drain that includes a channel region, a channel protection layer that covers only a portion of the area between the source and the drain, a source electrode that is brought into contact with the source contact area, and a drain electrode that is brought into contact with the drain contact area. At a cross-section in a channel length direction, of each TFT, an end portion facing toward the channel region, of one of the source and drain electrodes is brought into contact with the channel protection layer, and an end portion facing toward the channel region, of the other is positioned at a distance away from the channel protection layer.

Abstract: A semiconductor device includes a lower wiring layer formed on a substrate; a lower insulating layer formed on the lower wiring layer; an upper wiring layer formed on the lower insulating layer, the upper wiring layer intersecting with the lower wiring layer across the lower insulating layer to form a wiring cross portion; and an island-shaped upper insulating layer formed on the lower insulating layer so as to be in contact with the upper wiring layer, wherein the upper wiring layer includes a first portion formed on the upper face of the lower insulating layer and a second portion disposed on the wiring cross portion and formed on a side wall of the upper insulating layer, and wherein the upper wiring layer is not formed on the upper face of the upper insulating layer at the wiring cross portion.

Abstract: A semiconductor device includes a lower wiring layer formed on a substrate; a lower insulating layer formed on the lower wiring layer; an upper wiring layer formed on the lower insulating layer, the upper wiring layer intersecting with the lower wiring layer across the lower insulating layer to form a wiring cross portion; and an island-shaped upper insulating layer formed on the lower insulating layer so as to be in contact with the upper wiring layer, wherein the upper wiring layer includes a first portion formed on the upper face of the lower insulating layer and a second portion disposed on the wiring cross portion and formed on a side wall of the upper insulating layer, and wherein the upper wiring layer is not formed on the upper face of the upper insulating layer at the wiring cross portion.

Abstract: A semiconductor device includes a substrate; a gate electrode provided on the substrate; a first insulating layer formed on the gate electrode; an island-shaped oxide semiconductor layer formed on the first insulating layer; a source electrode electrically connected to the oxide semiconductor layer; and a drain electrode electrically connected to the oxide semiconductor layer, wherein the first insulating layer has a recess in the surface, wherein the oxide semiconductor layer is formed on a bottom surface and side walls of said recess and on an upper face of the first insulating layer, and wherein at least one of the source electrode and the drain electrode is disposed on a portion of the oxide semiconductor layer over the side walls of said recess, and is not formed on a portion of the oxide semiconductor layer over the upper face of the first insulating layer.

Abstract: A semiconductor device includes a substrate; a gate electrode provided on the substrate; a first insulating layer formed on the gate electrode; an island-shaped oxide semiconductor layer formed on the first insulating layer; a source electrode electrically connected to the oxide semiconductor layer; and a drain electrode electrically connected to the oxide semiconductor layer, wherein the first insulating layer has a recess in the surface, wherein the oxide semiconductor layer is formed on a bottom surface and side walls of said recess and on an upper face of the first insulating layer, and wherein at least one of the source electrode and the drain electrode is disposed on a portion of the oxide semiconductor layer over the side walls of said recess, and is not formed on a portion of the oxide semiconductor layer over the upper face of the first insulating layer.

Abstract: The present invention provides a semiconductor device which is provided with an oxide semiconductor TFT that can be reduced in the parasitic capacitance by suppressing process damage to a channel, while reducing the channel length (L). A semiconductor device of the present invention is provided with: a gate electrode (3) that is provided on a substrate (1); a first insulating layer (5) that is formed on the gate electrode (3); an island-shaped oxide semiconductor layer (7) that is formed on the first insulating layer (5); a source electrode (11) and a drain electrode (13) that are electrically connected to the oxide semiconductor layer (7); and a protective layer (9) that covers the upper surface of the oxide semiconductor layer (7). The source electrode (11) and/or the drain electrode (13) is arranged on a portion of the side faces of the oxide semiconductor layer (7) and a portion of the side faces of the protective layer (9), but does not cover the upper face of the protective layer (9).