Patents by Inventor Yuhide Yamamoto

Yuhide Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5898206
    Abstract: A MOSLSI in which a surface of a diffused layer is formed from silicide is improved in electrostatic breakdown voltage to raise the reliability thereof. The MOSLSI includes input and output protection elements each formed from MOS transistors. Each of the MOS transistors includes a field oxide film formed between a drain diffused layer and a gate electrode such that the gate electrode partially extends to a location on the field oxide film. A well having a conduction type same as that of the drain diffused layer is formed below a region which includes the field oxide film and the drain diffused layer. Since a lower portion of the field oxide film exhibits a high resistance, even if a silicide layer having a low resistance is formed on the surface of the diffused layer, the breakdown voltage of the transistor is maintained high. Consequently, local heat generation by a surge is prevented and a high electrostatic breakdown voltage can be achieved.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: April 27, 1999
    Assignee: NEC Corporation
    Inventor: Yuhide Yamamoto