Abstract: A semiconductor device includes a first stack of layers stacked on a substrate. The first stack of layers includes a source connection layer that is formed by replacing source sacrificial layers. The semiconductor device includes a channel structure that extends in the first stack of layers. The channel structure includes a channel layer that is in contact with the source connection layer in the first stack of layers. Further, the semiconductor device includes a shield structure formed in the first stack of layers. The shied structure encloses a stack of layers without the source connection layer.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a substrate, a plurality of gate layers, and a plurality of insulating layers. The plurality of gate layers and the plurality of insulating layers are stacked alternately over a first region of the substrate and are stacked of a stair-step form over a second region of the substrate. The semiconductor device also includes a channel structure that is disposed over the first region and through the plurality of gate layers and the plurality of insulating layers. The channel structure and the plurality of gate layers form a stack of transistors in a series configuration with the plurality of gate layers being a plurality of gates for the stack of transistors.

Abstract: A 3D memory device includes a memory stack and a support structure. The memory stack, on a substrate, includes a core region and a non-core region neighboring the core region. The support structure extends in the non-core region and into the substrate. The support structure includes a first support portion and a second support portion over the first support portion. The first support portion has a stiffness higher than the second support portion.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack and a plurality of memory strings. The memory stack includes interleaved conductive layers and dielectric layers. Each memory string extends vertically through the memory stack. The plurality of memory strings are divided into a plurality of regions of the memory stack in a plan view. The conductive layers include one or more drain select gate (DSG) lines configured to control drains of the plurality of memory strings. The numbers of the DSG lines are different among the plurality of regions. Each of the plurality of memory strings has a nominally same height.

Abstract: A three-dimensional memory includes a stack structure, a dummy structure and a gate line slit. The stack structure includes gate line layers and isolation layers stacked alternatively in the vertical direction. The dummy structure includes a first dummy section and a second dummy section. The gate line slit has one end extending into a gap formed by at least one of the first dummy section or the second dummy section. At least one of the first dummy section and the second dummy section partially overlaps a projection of the gate line slit onto the horizontal plane to realize connection between the dummy structure and the gate line slit.

Abstract: Aspects of the disclosure provide methods of manufacturing a semiconductor device. In a method, a stack of alternating gate layers and insulating layers is formed over a first region and a second region of a substrate of the semiconductor device. The stack of alternating gate layers and insulating layers is of a stair-step form over the second region of the substrate. A channel structure is formed over the first region and dummy channel structures are formed over the second region. The dummy channel structures includes a first dummy channel structure disposed through a first stair region of the stair-step form, a second dummy channel structure disposed through a second stair region of the stair-step form adjacent to the first stair region, and a third dummy channel structure disposed at a boundary between the first stair region and the second stair region.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack and a plurality of memory strings. The memory stack includes interleaved conductive layers and dielectric layers. Each memory string extends vertically through the memory stack. The plurality of memory strings are divided into a plurality of regions of the memory stack in a plan view. The conductive layers include one or more drain select gate (DSG) lines configured to control drains of the plurality of memory strings. The numbers of the DSG lines are different among the plurality of regions. Each of the plurality of memory strings has a nominally same height.

Abstract: A semiconductor device includes a first stack of layers stacked on a substrate. The first stack of layers includes a source connection layer that is formed by replacing source sacrificial layers. The semiconductor device includes a channel structure that extends in the first stack of layers. The channel structure includes a channel layer that is in contact with the source connection layer in the first stack of layers. Further, the semiconductor device includes a shield structure formed in the first stack of layers. The shied structure encloses a stack of layers without the source connection layer.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a substrate, a plurality of gate layers, and a plurality of insulating layers. The plurality of gate layers and the plurality of insulating layers are stacked alternately over a first region of the substrate and are stacked of a stair-step form over a second region of the substrate. The semiconductor device also includes a channel structure that is disposed over the first region and through the plurality of gate layers and the plurality of insulating layers. The channel structure and the plurality of gate layers form a stack of transistors in a series configuration with the plurality of gate layers being a plurality of gates for the stack of transistors.