Patents by Inventor Yuichi Egawa
Yuichi Egawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090179247Abstract: A technique which can improve manufacturing yield and product reliability is provided in a semiconductor device having a triple well structure. An inverter circuit which includes an n-channel type field effect transistor formed in a shallow p-type well and a p-channel type field effect transistor formed in a shallow n-type well, and does not contribute to circuit operations is provided in a deep n-type well formed in a p-type substrate; the shallow p-type well is connected to the substrate using a wiring of a first layer; and the gate electrode of the p-channel type field effect transistor and the gate electrode of the n-channel type field effect transistor are connected to the shallow n-type well using a wiring of an uppermost layer.Type: ApplicationFiled: January 15, 2009Publication date: July 16, 2009Inventors: Masako FUJII, Shigeki Obayashi, Naozumi Morino, Atsushi Hiraiwa, Shinichi Watarai, Takeshi Yoshida, Kazutoshi Oku, Masao Sugiyama, Yoshinori Kondo, Yuichi Egawa, Yoshiyuki Kaneko
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Publication number: 20050242377Abstract: A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOGOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure.Type: ApplicationFiled: June 30, 2005Publication date: November 3, 2005Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Kohei Eguchi, Yuichi Egawa, Shoichi Iwasa, Hideki Fujikake, Wataru Yokozeki, Tatsuya Kawamata
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Patent number: 6917076Abstract: A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOCOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure.Type: GrantFiled: July 31, 2003Date of Patent: July 12, 2005Assignee: United Microelectronics CorporationInventors: Kohei Eguchi, Yuichi Egawa, Shoichi Iwasa, Hideki Fujikake, Wataru Yokozeki, Tatsuya Kawamata
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Publication number: 20040262494Abstract: This invention provides a solid-state imaging device which enables its cell area to be reduced while maintaining a light receiving area. First, a plurality of isolation areas are formed in a semiconductor substrate. Then, p-type well is formed by implanting p-type impurity into the interior organization of an active area surrounded by the isolation areas. Next, by using ion implantation method, a charge accumulating area, which is a n-type semiconductor area, is formed deep in the p-type well. Consequently, photo diode is formed in a deep portion apart from the surface of the semiconductor substrate. After that, an electric transferring MIS transistor is formed above and apart from the charge accumulating area, so that the photo diode and the MIS transistor are formed in a vertical structure.Type: ApplicationFiled: June 23, 2004Publication date: December 30, 2004Applicant: Trecenti Technologies, Inc.Inventors: Yuichi Egawa, Akira Fukami
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Publication number: 20040173866Abstract: The invention provides a technology capable of preventing an excessive leak current in a pn junction of a photodiode. The n-type region of a photodiode is separated from a device isolating part and a p-type region of relatively high concentration is formed in such a way as to be in contact with the n-type region to reduce the effect which an interface state between the semiconductor substrate and the device isolating part or a stress caused by the crystal mismatching of a silicon single crystal constructing the semiconductor substrate produces on a depletion layer produced in the boundary between the n-type region and the p-type region of the photodiode, thereby reducing the leak current in the pn junction of the photodiode.Type: ApplicationFiled: December 24, 2003Publication date: September 9, 2004Inventors: Yuichi Egawa, Shuji IKeda
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Publication number: 20040021160Abstract: A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOCOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure.Type: ApplicationFiled: July 31, 2003Publication date: February 5, 2004Inventors: Kohei Eguchi, Yuichi Egawa, Shoichi Iwasa, Hideki Fujikake, Wataru Yokozeki, Tatsuya Kawamata
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Patent number: 6657229Abstract: A semiconductor device has field shield isolation or trench type isolation between elements which suppresses penetration of field oxide into an element active region of the device. A common gate is located between two MOS transistors, which may be of opposite conductivity type. After gate electrode wiring layers are formed in a field region and an active region to the same level, a pad polysilicon film formed on the entire surface to cover the patterns of these gate electrode wiring layers, which are in separated patterns.Type: GrantFiled: August 24, 1999Date of Patent: December 2, 2003Assignee: United Microelectronics CorporationInventors: Kohei Eguchi, Yuichi Egawa, Shoichi Iwasa, Hideki Fujikake, Wataru Yokozeki, Tatsuya Kawamata
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Patent number: 6118145Abstract: A semiconductor device with a reduced slope between components, and a method of manufacturing a semiconductor device, represented by DRAM, having a large difference of level between components, for planarizing an inter-layer insulating film covering respective components in accordance with a design to precisely reduce a slope of the inter-layer insulating film over the difference in level between components, without increasing the number of manufacturing steps or introducing complicated manufacturing steps. Each storage node electrode connected to a source is formed, and an electrically isolated dummy pattern is simultaneously formed on an inter-layer insulating film. Then, a BPSG film is formed and reflowed, followed by etching back the surface of the BPSG film. Subsequently, the dummy pattern is used as an index for indicating the end of the etch back, and the BPSG film is etched back until a portion of a cell plate electrode covering the dummy pattern is exposed.Type: GrantFiled: June 22, 1998Date of Patent: September 12, 2000Assignee: Nippon Steel CorporationInventor: Yuichi Egawa
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Patent number: 6066886Abstract: Redundant memory portions having redundant memory cells for relieving malfunctioning normal memory cells are arranged among the semiconductor memory portions that neighbor each other in the row direction and in the column direction on a semiconductor wafer on which a plurality of semiconductor memory portions are arranged in the form of a matrix. Cutting lines are formed between the redundant memory portions and the neighboring semiconductor memory portions, so that the semiconductor wafer can be separated into semiconductor memory devices (chips) in a subsequent stage in a manner in which the redundant memory portions are connected to the semiconductor memory portion as required. This embodiment makes it possible to decrease the chip size and to efficiently substitute the redundant memory cell array for the defective lines.Type: GrantFiled: October 27, 1997Date of Patent: May 23, 2000Assignee: United MicroelectronicsInventor: Yuichi Egawa
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Patent number: 5770874Abstract: A high density semiconductor memory device includes: a semiconductor substrate; and a plurality of memory cell groups formed on the semiconductor substrate, each of the memory cell groups including a plurality of memory cells having one common source/drain region, wherein when a surface of the semiconductor substrate is divided into a plurality of areas which are arranged in a matrix of rows extending in a first direction and columns extending in a second direction intersecting the first direction, the memory cell groups are selectively arranged in the areas such that the memory cell groups are located in every other one of the areas arranged in each of the rows and also in every other one of the areas arranged in each of the columns.Type: GrantFiled: November 10, 1997Date of Patent: June 23, 1998Assignee: Nippon Steel CorporationInventor: Yuichi Egawa
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Patent number: 5438214Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed in which the method comprises the steps of forming an insulating film for element-isolation and a gate insulating film on a surface of a semiconductor substrate, forming a semiconductor film on the element-isolation insulating film and the gate insulating film, removing a part of the semiconductor film corresponding to a boundary between a first region for formation of an N-channel transistor and a second region for formation of a P-channel transistor, introducing N type impurities into a part of the semiconductor film located on the first region and introducing P type impurities into a part of the semiconductor film located on the second region, forming a metallic film over the semiconductor film having the impurities introduced therein and the element-isolation insulating film, and patterning the metallic film and the semiconductor film into a pattern of a gate electrode common to the N-channel transistor and the P-chaType: GrantFiled: May 31, 1994Date of Patent: August 1, 1995Assignee: Nippon Steel CorporationInventors: Yuichi Egawa, Yasuo Sato
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Patent number: 5436481Abstract: A MOS semiconductor device and a method of making the same are arranged to include a semiconductor substrate of a first conductivity type; a pair of impurity diffused layers of a second conductivity type different from the first conductivity type formed in the semiconductor substrate and mutually separated by a distance of 0.1 .mu.m or less; a gate insulating film including at least two layers of a silicon oxide film and a silicon nitride film and formed on a portion of the semiconductor substrate disposed between the pair of impurity diffused layers; and a gate electrode formed on the gate insulating film, wherein preferably the silicon nitride film has a thickness of 4.5 nm to 14.86 nm.Type: GrantFiled: January 19, 1994Date of Patent: July 25, 1995Assignee: Nippon Steel CorporationInventors: Yuichi Egawa, Toshio Wada, Shoichi Iwasa
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Patent number: 5424978Abstract: A non-volatile semiconductor memory device capable of selectively storing one of at least three different data comprises a memory array including a plurality of memory cells, each having a control gate, a floating gate, a drain, and a source, a circuit for producing a stepped voltage whose level is varied stepwise to a number of different levels corresponding to a number of data to be stored, a circuit for producing a pulse voltage having a predetermined voltage level and a predetermined pulse width, and a circuit for selecting one of the plurality of memory cells, wherein during storing of the at least three different data the stepped voltage and the pulse voltage are applied to the control gate and the drain of the selected memory cell, respectively, while a timing of application of the pulse voltage to the drain is controlled relative to a timing of application of the stepped voltage to the control gate, depending on which of the at least three different data is to be stored into the selected memory cell.Type: GrantFiled: March 14, 1994Date of Patent: June 13, 1995Assignee: Nippon Steel CorporationInventors: Toshio Wada, Kenji Anzai, Shoichi Iwasa, Yasuo Sato, Yuichi Egawa
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Patent number: 5313418Abstract: A mask ROM of the invention comprises: a plurality of memory cells arranged m a matrix; a plurality of word lines, each connecting gates of the memory cells in the lateral direction; a plurality of bit lines which are constructed by serially connecting MOS transistors constructing the memory cells; a row decoder connected to the word lines; and a column decoder connected to the bit lines in which each memory cell is constructed by an MOS transistor and a resistor connected in parallel between the source and drain of each MOS transistor. The content of each memory cell is determined by whether the resistor 8 is cut out or not so that the steps up to the cutting step of the resistors 8 can be standardized while maintaining a high density in integration of the memory cells and the turn-around time can be reduced.Type: GrantFiled: October 28, 1992Date of Patent: May 17, 1994Assignee: Nippon SteelInventors: Toshio Wada, Yuichi Egawa