Abstract: Apparatuses may include a memory block with strings of memory cells formed in a plurality of tiers. The apparatus may further comprise access lines and data lines shared by the strings, with the access lines coupled to the memory cells corresponding to a respective tier of the plurality of tiers. The memory cells corresponding to at least a portion of the respective tier may comprise a respective page of a plurality of pages. Subsets of the data lines may be mapped into a respective partial page of a plurality of partial pages of the respective page. Each partial page may be independently selectable from other partial pages. Additional apparatuses and methods are disclosed.

Abstract: Apparatuses may include a memory block with strings of memory cells formed in a plurality of tiers. The apparatus may further comprise access lines and data lines shared by the strings, with the access lines coupled to the memory cells corresponding to a respective tier of the plurality of tiers. The memory cells corresponding to at least a portion of the respective tier may comprise a respective page of a plurality of pages. Subsets of the data lines may be mapped into a respective partial page of a plurality of partial pages of the respective page. Each partial page may be independently selectable from other partial pages. Additional apparatuses and methods are disclosed.

Abstract: Apparatuses may include a memory block with strings of memory cells formed in a plurality of tiers. The apparatus may further comprise access lines and data lines shared by the strings, with the access lines coupled to the memory cells corresponding to a respective tier of the plurality of tiers. The memory cells corresponding to at least a portion of the respective tier may comprise a respective page of a plurality of pages. Subsets of the data lines may be mapped into a respective partial page of a plurality of partial pages of the respective page. Each partial page may be independently selectable from other partial pages. Additional apparatuses and methods are disclosed.

Abstract: Apparatuses may include a memory block with strings of memory cells formed in a plurality of tiers. The apparatus may further comprise access lines and data lines shared by the strings, with the access lines coupled to the memory cells corresponding to a respective tier of the plurality of tiers. The memory cells corresponding to at least a portion of the respective tier may comprise a respective page of a plurality of pages. Subsets of the data lines may be mapped into a respective partial page of a plurality of partial pages of the respective page. Each partial page may be independently selectable from other partial pages. Additional apparatuses and methods are disclosed.

Abstract: A semiconductor memory that prevents a decrease in margin at read time. A bit line in a floating state between a drain in a memory cell to be read and a charged bit line is charged for a certain period of time.

Abstract: A semiconductor memory that prevents a decrease in margin at read time. A bit line in a floating state between a drain in a memory cell to be read and a charged bit line is charged for a certain period of time.

Abstract: A semiconductor memory comprises a p-type silicon substrate including a first diffused layer and a second diffused layer, and a gate insulation film in which carriers are trapped in different areas. A first voltage and a second voltage are applied to the p-type silicon substrate and the gate electrode, respectively, to allow tunnel current to flow between the p-type silicon substrate and the gate electrode so that the tunnel current may eliminate the carriers trapped in the gate insulation film. This allows all the electrons captured in the central portion of the channel area to disappear, resulting in more reliable data erasure.

Abstract: Nonvolatile semiconductor memory has a core-side cell array having word lines, bit lines and memory cells; a reference-side cell array having word lines, bit line, and reference cell; and, a sense amplifier which compares a core-side input voltage corresponding to a bit line current in the core-side cell array, and a reference-side input voltage corresponding to the bit-line current in the reference-side cell array. The core-side decoder-driver and reference-side decoder-driver drive the core-side and reference-side word lines to the power supply voltage at a first time at the end of the address change detection pulse, and, at a second time a prescribed time after the end of the address change detection pulse, drive the core-side and reference-side word lines to a boost voltage level higher than the power supply voltage. The sense amplifier begins comparison of the core-side and the reference-side input voltages after the second time.

Abstract: Nonvolatile semiconductor memory has a core-side cell array having word lines, bit lines and memory cells; a reference-side cell array having word lines, bit line, and reference cell; and, a sense amplifier which compares a core-side input voltage corresponding to a bit line current in the core-side cell array, and a reference-side input voltage corresponding to the bit-line current in the reference-side cell array. The core-side decoder-driver and reference-side decoder-driver drive the core-side and reference-side word lines to the power supply voltage at a first time at the end of the address change detection pulse, and, at a second time a prescribed time after the end of the address change detection pulse, drive the core-side and reference-side word lines to a boost voltage level higher than the power supply voltage. The sense amplifier begins comparison of the core-side and the reference-side input voltages after the second time.

Abstract: A semiconductor memory comprises a p-type silicon substrate including a first diffused layer and a second diffused layer, and a gate insulation film in which carries are trapped in different areas. A first voltage and a second voltage are applied to the p-type silicon substrate and the gate electrode, respectively, to allow tunnel current to flow between the p-type silicon substrate and the gate electrode so that the tunnel current may eliminate the carries trapped in the gate insulation film. This allows all the electrons captured in the central portion of the channel area to disappear, resulting in more reliable data erasure.

Abstract: A voltage raising circuit of a semiconductor memory includes a compensating circuit. The compensating circuit has a negative dependency on a source voltage for controlling a variation of a raised voltage caused by a variation of the source voltage, and a positive dependency on temperature for controlling a variation of the raised voltage caused by a variation of the temperature.

Abstract: A voltage raising circuit of a semiconductor memory includes a compensating circuit. The compensating circuit has a negative dependency on a source voltage for controlling a variation of a raised voltage caused by a variation of the source voltage, and a positive dependency on temperature for controlling a variation of the raised voltage caused by a variation of the temperature.