Patents by Inventor Yuichi Fukuda

Yuichi Fukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935339
    Abstract: Provided are a vehicle inspection system and a vehicle inspection method that can align a vehicle with a constant location of a bench testing machine. The present invention comprises: a bench testing machine that rotatably supports wheels of a vehicle, using rollers that are provided for each of the wheels; and a monitor device that is positioned in a fixed location with regard to the bench testing machine and displays, toward a camera, an image resembling an exterior environment, wherein the bench testing machine has a location adjustment device (turning mechanism, test bench control device) that adjusts the location of the vehicle in the vehicle width direction such that the relative location of the camera in the vehicle width direction with regard to the monitor device is constant.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: March 19, 2024
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Kento Aono, Tatsuya Jitsui, Kenichiro Kurai, Yuichi Fukuda, Yasushi Watanabe
  • Publication number: 20230218612
    Abstract: The present invention provides a nitrogen-containing heterocyclic compound or a pharmaceutically acceptable salt thereof having an inhibitory effect on the production of kynurenine, represented by formula (I): (wherein R6 and R7 may be the same or different and each represent a hydrogen atom or the like, R8, R9, R10, and R11 may be the same or different and each represent a hydrogen atom or the like, R1 represents lower alkyl which may be substituted with cycloalkyl, or the like, and R3 represents optionally substituted aryl or an optionally substituted heterocyclic group).
    Type: Application
    Filed: March 8, 2023
    Publication date: July 13, 2023
    Applicant: Kyowa Kirin Co., Ltd.
    Inventors: Yuichi FUKUDA, Toshimi KANAI, Yoshisuke NAKASATO, Keisuke KIMPARA
  • Patent number: 11648156
    Abstract: A urine absorption pad for preventing leakage of urine is provided. A urine absorption pad includes: a front surface sheet (16) which has water permeability and contacts a skin; a back surface sheet (17) which has water impermeability and contacts underwear; an absorbent (18) which is sandwiched between the front surface sheet (16) and the back surface sheet (17) and absorbs urine having passed through the front surface sheet (16); and a guide A (11) and a guide B (12) which allow urine to permeate and are self-standing so as to rise to the front surface sheet (16) side with respect to the absorbent (18) to control flow of urine. The guide A (11) is arranged at an edge portion, and the guide B (12) is arranged so as to extend in a left-right direction.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: May 16, 2023
    Assignee: IP GIKEN LLC
    Inventor: Yuichi Fukuda
  • Publication number: 20220378629
    Abstract: A urine absorption pad for preventing leakage of urine is provided. A urine absorption pad includes: a front surface sheet (16) which has water permeability and contacts a skin; a back surface sheet (17) which has water impermeability and contacts underwear; an absorbent (18) which is sandwiched between the front surface sheet (16) and the back surface sheet (17) and absorbs urine having passed through the front surface sheet (16); and a guide A (11) and a guide B (12) which allow urine to permeate and are self-standing so as to rise to the front surface sheet (16) side with respect to the absorbent (18) to control flow of urine. The guide A (11) is arranged at an edge portion, and the guide B (12) is arranged so as to extend in a left-right direction.
    Type: Application
    Filed: August 5, 2022
    Publication date: December 1, 2022
    Applicant: IP GIKEN LLC
    Inventor: Yuichi FUKUDA
  • Publication number: 20210287460
    Abstract: Provided are a vehicle inspection system and a vehicle inspection method that can align a vehicle with a constant location of a bench testing machine. The present invention comprises: a bench testing machine that rotatably supports wheels of a vehicle, using rollers that are provided for each of the wheels; and a monitor device that is positioned in a fixed location with regard to the bench testing machine and displays, toward a camera, an image resembling an exterior environment, wherein the bench testing machine has a location adjustment device (turning mechanism, test bench control device) that adjusts the location of the vehicle in the vehicle width direction such that the relative location of the camera in the vehicle width direction with regard to the monitor device is constant.
    Type: Application
    Filed: September 10, 2019
    Publication date: September 16, 2021
    Inventors: Kento Aono, Tatsuya Jitsui, Kenichiro Kurai, Yuichi Fukuda, Yasushi Watanabe
  • Patent number: 10745700
    Abstract: The present invention relates to a nucleic acid conjugate represented by the following formula 1: wherein X is an oligonucleotide, L1 and L2 are each independently sugar ligand, and S1, S2 and S3 are each independently a linker.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: August 18, 2020
    Assignee: KYOWA KIRIN CO., LTD.
    Inventors: Keiji Uehara, Yasuhiro Suzuki, Hiroto Iwai, Masakazu Homma, Yuichi Fukuda, Tatsuto Kiuchi
  • Publication number: 20200179376
    Abstract: The present invention provides a nitrogen-containing heterocyclic compound or a pharmaceutically acceptable salt thereof having an inhibitory effect on the production of kynurenine, represented by formula (I): (wherein R6 and R7 may be the same or different and each represent a hydrogen atom or the like, R8, R9, R10, and R11 may be the same or different and each represent a hydrogen atom or the like, R1 represents lower alkyl which may be substituted with cycloalkyl, or the like, and R3 represents optionally substituted aryl or an optionally substituted heterocyclic group).
    Type: Application
    Filed: December 4, 2019
    Publication date: June 11, 2020
    Applicant: Kyowa Kirin Co., Ltd.
    Inventors: Yuichi Fukuda, Toshimi Kanai, Yoshisuke Nakasato, Keisuke Kimpara
  • Patent number: 10548891
    Abstract: The present invention provides a nitrogen-containing heterocyclic compound or a pharmaceutically acceptable salt thereof having an inhibitory effect on the production of kynurenine, represented by formula (I): (wherein R6 and R7 may be the same or different and each represent a hydrogen atom or the like, R8, R9, R10, and R11 may be the same or different and each represent a hydrogen atom or the like, R1 represents lower alkyl which may be substituted with cycloalkyl, or the like, and R3 represents optionally substituted aryl or an optionally substituted heterocyclic group).
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: February 4, 2020
    Assignee: KYOWA HAKKO KIRIN CO., LTD.
    Inventors: Yuichi Fukuda, Toshimi Kanai, Yoshisuke Nakasato, Keisuke Kimpara
  • Patent number: 10220904
    Abstract: To avoid causing significant damage to a temperature sensor or an unintentional shift of the temperature sensor, a hand grip disclosed herein includes: a cylindrical inner housing 110; a heating element 120 provided adjacent to an outer peripheral side of the inner housing 110; a temperature sensor 140 provided adjacent to the outer peripheral side of the inner housing 110; and a sheathing 130 covering the inner housing 110, the heating element 120, and the temperature sensor 140. A recess 111 is formed on an outer peripheral surface of the inner housing 110, and the temperature sensor 140 is fitted into the recess 111.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: March 5, 2019
    Assignee: FALTEC CO., LTD.
    Inventors: Kouzo Sasaki, Yuichi Fukuda, Shigeki Koyanagi, Kaoru Saito
  • Publication number: 20190055558
    Abstract: The present invention relates to a nucleic acid conjugate represented by the following formula 1: wherein X is an oligonucleotide, L1 and L2 are each independently sugar ligand, and S1, S2 and S3 are each independently a linker.
    Type: Application
    Filed: January 30, 2017
    Publication date: February 21, 2019
    Applicant: Kyowa Hakko Kirin Co., Ltd.
    Inventors: Keiji UEHARA, Yasuhiro SUZUKI, Hiroto IWAI, Masakazu HOMMA, Yuichi FUKUDA, Tatsuto KIUCHI
  • Publication number: 20180194420
    Abstract: To avoid causing significant damage to a temperature sensor or an unintentional shift of the temperature sensor, a hand grip disclosed herein includes: a cylindrical inner housing 110; a heating element 120 provided adjacent to an outer peripheral side of the inner housing 110; a temperature sensor 140 provided adjacent to the outer peripheral side of the inner housing 110; and a sheathing 130 covering the inner housing 110, the heating element 120, and the temperature sensor 140. A recess 111 is formed on an outer peripheral surface of the inner housing 110, and the temperature sensor 140 is fitted into the recess 111.
    Type: Application
    Filed: March 28, 2016
    Publication date: July 12, 2018
    Inventors: Kouzo SASAKI, Yuichi FUKUDA, Shigeki KOYANAGI, Kaoru SAITO
  • Patent number: 9858181
    Abstract: A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: January 2, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Uematsu, Satoshi Muraoka, Hiroshi Kakita, Akio Idei, Yusuke Fukumura, Satoru Watanabe, Takayuki Ono, Taishi Sumikura, Yuichi Fukuda, Takashi Miyagawa, Michinori Naito, Hideki Osaka, Masabumi Shibata, Hitoshi Ueno, Kazunori Nakajima, Yoshihiro Kondo
  • Patent number: 9658783
    Abstract: In methods connecting a memory module configured from DRAM, which is high-speed memory, and a memory module configured from flash memory which is slower than DRAM but is high-capacity memory, to a CPU memory bus, in the case of sequential reading, the busy rate of the CPU memory bus increases, and performance degradation occurs easily. In the present invention, an information processing device has a CPU, a CPU memory bus, and a primary storage device. The primary storage device has a first memory module and a second memory module. The first memory module has high-speed memory. The second memory module has memory having the same memory interface as that of the high-speed memory, high-capacity memory having a different memory interface from that of the high-speed memory, and a controller that controls same. The first memory module and second memory module are caused to be accessed by the memory interface of the high-speed memory.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: May 23, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Muraoka, Yutaka Uematsu, Hideki Osaka, Yuusuke Fukumura, Satoru Watanabe, Masabumi Shibata, Hiroshi Kakita, Yuichi Fukuda, Takashi Miyagawa, Michinori Naito, Hitoshi Ueno, Akio Idei, Takayuki Ono, Taishi Sumikura
  • Patent number: 9569144
    Abstract: When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: February 14, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Uematsu, Satoshi Muraoka, Hideki Osaka, Masabumi Shibata, Yuusuke Fukumura, Satoru Watanabe, Hiroshi Kakita, Akio Idei, Hitoshi Ueno, Takayuki Ono, Takashi Miyagawa, Michinori Naito, Taishi Sumikura, Yuichi Fukuda
  • Publication number: 20160092351
    Abstract: A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed.
    Type: Application
    Filed: June 20, 2013
    Publication date: March 31, 2016
    Inventors: Yutaka UEMATSU, Satoshi MURAOKA, Hiroshi KAKITA, Akio IDEI, Yusuke FUKUMURA, Satoru WATANABE, Takayuki ONO, Taishi SUMIKURA, Yuichi FUKUDA, Takashi MIYAGAWA, Michinori NAITO, Hideki OSAKA, Masabumi SHIBATA, Hitoshi UENO, Kazunori NAKAJIMA, Yoshihiro KONDO
  • Publication number: 20150352106
    Abstract: The present invention provides a nitrogen-containing heterocyclic compound or a pharmaceutically acceptable salt thereof having an inhibitory effect on the production of kynurenine, represented by formula (I): (wherein R6 and R7 may be the same or different and each represent a hydrogen atom or the like, R8, R9, R10, and R11 may be the same or different and each represent a hydrogen atom or the like, R1 represents lower alkyl which may be substituted with cycloalkyl, or the like, and R3 represents optionally substituted aryl or an optionally substituted heterocyclic group).
    Type: Application
    Filed: August 17, 2015
    Publication date: December 10, 2015
    Inventors: Yuichi FUKUDA, Toshimi Kanai, Yoshisuke Nakasato, Keisuke Kimpara
  • Publication number: 20150355846
    Abstract: When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.
    Type: Application
    Filed: March 27, 2013
    Publication date: December 10, 2015
    Inventors: Yutaka UEMATSU, Satoshi MURAOKA, Hideki OSAKA, Masabumi SHIBATA, Yuusuke FUKUMURA, Satoru WATANABE, Hiroshi KAKITA, Akio IDEI, Hitoshi UENO, Takayuki ONO, Takashi MIYAGAWA, Michinori NAITO, Taishi SUMIKURA, Yuichi FUKUDA
  • Publication number: 20150347032
    Abstract: In methods connecting a memory module configured from DRAM, which is high-speed memory, and a memory module configured from flash memory which is slower than DRAM but is high-capacity memory, to a CPU memory bus, in the case of sequential reading, the busy rate of the CPU memory bus increases, and performance degradation occurs easily. In the present invention, an information processing device has a CPU, a CPU memory bus, and a primary storage device. The primary storage device has a first memory module and a second memory module. The first memory module has high-speed memory. The second memory module has memory having the same memory interface as that of the high-speed memory, high-capacity memory having a different memory interface from that of the high-speed memory, and a controller that controls same. The first memory module and second memory module are caused to be accessed by the memory interface of the high-speed memory.
    Type: Application
    Filed: March 27, 2013
    Publication date: December 3, 2015
    Inventors: Satoshi MURAOKA, Yutaka UEMATSU, Hideki OSAKA, Yuusuke FUKUMURA, Satoru WATANABE, Masabumi SHIBATA, Hiroshi KAKITA, Yuichi FUKUDA, Takashi MIYAGAWA, Michinori NAITO, Hitoshi UENO, Akio IDEI, Takayuki ONO, Taishi SUMIKURA
  • Patent number: D869995
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: December 17, 2019
    Assignee: FALTEC Co., Ltd.
    Inventor: Yuichi Fukuda
  • Patent number: D918782
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: May 11, 2021
    Assignee: FALTEC Co., Ltd.
    Inventor: Yuichi Fukuda