Patents by Inventor Yuichi Hamamura

Yuichi Hamamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6960765
    Abstract: A probe driving method and a probe apparatus for bringing a probe into contact with the surface of a sample in a safe and efficient manner by monitoring the probe height. Information about the height of the probe from the sample surface is obtained by detecting a probe shadow appearing immediately before the probe contacts the sample, or based on a change in relative positions of a probe image and a sample image that are formed as an ion beam is irradiated diagonally.
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: November 1, 2005
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Satoshi Tomimatsu, Hidemi Koike, Junzo Azuma, Tohru Ishitani, Aritoshi Sugimoto, Yuichi Hamamura, Isamu Sekihara, Akira Shimase
  • Patent number: 6895346
    Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: May 17, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Kazuyuki Tsunokuni, Aritoshi Sugimoto
  • Patent number: 6841405
    Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: January 11, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
  • Patent number: 6780660
    Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: August 24, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
  • Patent number: 6770496
    Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: August 3, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
  • Patent number: 6771077
    Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: August 3, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
  • Publication number: 20030197523
    Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
    Type: Application
    Filed: October 10, 2002
    Publication date: October 23, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
  • Publication number: 20030199107
    Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
    Type: Application
    Filed: April 19, 2002
    Publication date: October 23, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Kazuyuki Tsunokuni, Aritoshi Sugimoto
  • Publication number: 20030199110
    Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
    Type: Application
    Filed: October 10, 2002
    Publication date: October 23, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Kazuyuki Tsunokuni, Aritoshi Sugimoto
  • Publication number: 20030197522
    Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
    Type: Application
    Filed: October 10, 2002
    Publication date: October 23, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
  • Publication number: 20030199111
    Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
    Type: Application
    Filed: October 10, 2002
    Publication date: October 23, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
  • Publication number: 20030184332
    Abstract: A probe driving method and a probe apparatus for bringing a probe into contact with the surface of a sample in a safe and efficient manner by monitoring the probe height. Information about the height of the probe from the sample surface is obtained by detecting a probe shadow (54) appearing immediately before the probe contacts the sample, or based on a change in relative positions of a probe image and a sample image that are formed as an ion beam is irradiated diagonally.
    Type: Application
    Filed: November 29, 2002
    Publication date: October 2, 2003
    Inventors: Satoshi Tomimatsu, Hidemi Koike, Junzo Azuma, Tohru Ishitani, Aritoshi Sugimoto, Yuichi Hamamura, Isamu Sekihara, Akira Shimase
  • Patent number: 6476387
    Abstract: In a method for observing or processing and analyzing the surface of a sample by irradiating a charged beam on the sample covered at least partially by an insulator film, an ultraviolet light is irradiated possibly as pulse on the sample (substrate), thereby transforming the insulator into a conductive material due to the photoconductivity effect, thereby transforming the surface of the sample (substrate) into a conductive material, so that charged particles are grounded from a grounded portion in order to prevent the charged beam from being repulsed due to charged particles of the irradiated charged beam accumulated in the insulator formed on the surface of the sample (substrate).
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: November 5, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Norimasa Nishimura, Akira Shimase, Junzou Azuma, Yuichi Hamamura, Michinobu Mizumura, Yasuhiro Koizumi, Hidemi Koike
  • Patent number: 6344115
    Abstract: A pattern forming method using an improved charged particle beam process, and a charged particle beam processing system prevent effectively the corrosion of a workpiece by a reactive gas adsorbed by and adhering to the surface of the workpiece when the workpiece is taken out into the atmosphere after pattern formation. The charged particle beam processing system comprises, as principal components, an ion beam chamber provided with an ion beam optical system, a processing chamber provided with a gas nozzle through which a reactive gas is blown against a workpiece, a load-lock chamber connected through a gate valve to the processing chamber. The load-lock chamber is capable of producing a plasma of an inert gas for processing the surface of the workpiece by sputtering.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: February 5, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Junzou Azuma, Akira Shimase, Yuichi Hamamura, Hidemi Koike
  • Patent number: 6303932
    Abstract: A secondary charged particle image acquisition method and its apparatus for detecting a secondary charged particle image. The method includes the steps of irradiating a surface of a specimen with a focused charged particle beam and detecting a secondary charged particle emanated from the surface of the specimen, obtaining a secondary charged particle image based on the detected secondary charged particle, irradiating a positive ion beam on the surface of the specimen where the focused charged particle beam is irradiated and inducing a conductive layer on the surface of the specimen by the irradiation of the positive ion beam and diffusing an electric charge on the surface of the conductive layer.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: October 16, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Akira Shimase, Junzou Azuma, Michinobu Mizumura, Norimasa Nishimura, Yasuhiro Koizumi, Hidemi Koike
  • Publication number: 20010016061
    Abstract: In order to allow critical flaws in an inspected item to be known early during a production process, the present invention includes the following steps: a step for detecting defects in a production process for the inspected item and storing defect positions; a step for collecting detailed defect information and storing the detailed information in association with defect positions; a step for storing positions at which flaws were generated based on a final inspection of the inspected item; a step for comparing defect positions with positions at which flaws were generated; and a step for classifying and displaying information based on the comparison results.
    Type: Application
    Filed: February 15, 2001
    Publication date: August 23, 2001
    Inventors: Atsushi Shimoda, Ichirou Ishimaru, Yuji Takagi, Takuo Tamura, Yuichi Hamamura, Kenji Watanabe, Yasuhiko Ozawa, Seiji Isogai
  • Patent number: 5976328
    Abstract: A pattern forming method using an improved charged particle beam process, and a charged particle beam processing system prevent effectively the corrosion of a workpiece by a reactive gas adsorbed by and adhering to the surface of the workpiece when the workpiece is taken out into the atmosphere after pattern formation. The charged particle beam processing system comprises, as principal components, an ion beam chamber provided with an ion beam optical system, a processing chamber (18) provided with a gas nozzle through which a reactive gas is blown against a workpiece, a load-lock chamber connected through a gate valve to the processing chamber. The load-lock chamber is capable of producing a plasma of an inert gas for processing the surface of the workpiece by sputtering.
    Type: Grant
    Filed: January 27, 1997
    Date of Patent: November 2, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Junzou Azuma, Akira Shimase, Yuichi Hamamura, Hidemi Koike
  • Patent number: 5952658
    Abstract: A charged particle beam milling system which is designed in such a way that a milling end point is judged to stop the milling on the basis of a change in the magnitude of secondary ion signals generated when milling an electronic device such as an LSI having a multi-wiring layer structure, in which a wiring layer and an insulating layer are laminated, using a charged particle beam.
    Type: Grant
    Filed: April 18, 1997
    Date of Patent: September 14, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Akira Shimase, Yuichi Hamamura, Junzou Azuma, Michinobu Mizumura