Patents by Inventor Yuichi Harada

Yuichi Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240127830
    Abstract: This encoding device comprises: a downmix circuit that switches mixing processing according to the characteristic of an input stereo signal to generate either a first stereo signal or a second stereo signal obtained by mixing processing of a left channel signal and a right channel signal; a first encoding circuit that encodes the first stereo signal; and a second encoding circuit that encodes two signals included in the second stereo signal. The second encoding circuit performs monaural encoding on the basis of the encoding mode of the first encoding circuit in a first section in which switching from the first stereo signal to the second stereo signal is performed and/or a second section in which switching from the second stereo signal to the first stereo signal is performed.
    Type: Application
    Filed: October 15, 2021
    Publication date: April 18, 2024
    Applicant: Panasonic Intellectual Property Corporation of America
    Inventors: Yuichi KAMIYA, Takuya KAWASHIMA, Akira HARADA, Hiroyuki EHARA
  • Publication number: 20240116943
    Abstract: The present invention provides a compound having a Pim-1 inhibitory activity. The present invention provides a compound of Formula [I] or a pharmaceutically acceptable salt thereof, a pharmaceutical composition containing the same, and a pharmaceutical use thereof, and the like. wherein each symbol is as defined in the description.
    Type: Application
    Filed: March 21, 2023
    Publication date: April 11, 2024
    Inventors: Masafumi Inoue, Yosuke Ogoshi, Takayuki Furukawa, Takuya Machida, Ikuo Mitani, Kazuhito Harada, Yuichi Nakagawa, Nobutaka Yamaoka
  • Patent number: 11949005
    Abstract: Provided is a semiconductor device that includes a first conductivity type well region below a gate runner portion, wherein a diode region includes first contact portions, a first conductivity type anode region, and a second conductivity type cathode region; wherein the well region contacts the diode region in the first direction, and when an end of the well region, an end of at least one of first contact portions, and an end of the cathode region that face one another in the first direction are imaginary projected on an upper surface of the semiconductor substrate, a first distance is longer than a second distance, the first distance being a distance between the end of the well region and the end of the cathode region, and the second distance being a distance between the end of the well region and the end of the at least one first contact portion.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: April 2, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Misaki Takahashi, Yuichi Harada, Kouta Yokoyama
  • Publication number: 20230360915
    Abstract: A semiconductor device including a semiconductor substrate having an upper surface and a lower surface is provided. In a depth direction connecting the upper and lower surfaces of the semiconductor substrate, a donor concentration distribution includes a first donor concentration peak at a first depth, a second donor concentration peak at a second depth between the first donor concentration peak and the upper surface, a flat region between the first donor concentration peak and the second donor concentration peak, and a plurality of donor concentration peaks between the first donor concentration peak and the lower surface. The second donor concentration peak has a lower concentration than the first donor concentration peak. The donor concentration distribution in the flat region is substantially flat. The thickness of the flat region in the depth direction is 10% or more of the thickness of the semiconductor substrate.
    Type: Application
    Filed: July 20, 2023
    Publication date: November 9, 2023
    Inventors: Yasunori AGATA, Takashi YOSHIMURA, Hiroshi TAKISHITA, Misaki MEGURO, Naoko KODAMA, Yoshihiro IKURA, Seiji NOGUCHI, Yuichi HARADA, Yosuke SAKURAI
  • Publication number: 20230307446
    Abstract: Provided is a semiconductor device comprising a semiconductor substrate that includes a transistor region; an emitter electrode that is provided on the semiconductor substrate; a first dummy trench portion that is provided on the transistor region of the semiconductor substrate and includes a dummy conducting portion that is electrically connected to the emitter electrode; and a first contact portion that is a partial region of the transistor region, provided between an end portion of a long portion of the first dummy trench portion and an end portion of the semiconductor substrate, and electrically connects the emitter electrode and a semiconductor region with a first conductivity type provided in the transistor region.
    Type: Application
    Filed: April 11, 2023
    Publication date: September 28, 2023
    Inventor: Yuichi HARADA
  • Patent number: 11735424
    Abstract: A semiconductor device comprising a semiconductor substrate including an upper surface and a lower surface wherein a donor concentration of a drift region is higher than a base doping concentration of the semiconductor substrate, entirely over the drift region in a depth direction connecting the upper surface and the lower surface is provided.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: August 22, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasunori Agata, Takashi Yoshimura, Hiroshi Takishita, Misaki Meguro, Naoko Kodama, Yoshihiro Ikura, Seiji Noguchi, Yuichi Harada, Yosuke Sakurai
  • Publication number: 20230144542
    Abstract: Provided is a manufacturing method of a semiconductor device, the manufacturing method including implanting a first dopant of a first conductivity type from an implantation surface of a semiconductor substrate into a first implantation position and implanting a second dopant of the first conductivity type from the implantation surface of the semiconductor substrate into a second implantation position having a larger distance from the implantation surface than the first implantation position after implanting the first dopant. The first implantation position and the second implantation position may be arranged in the buffer region.
    Type: Application
    Filed: October 24, 2022
    Publication date: May 11, 2023
    Inventors: Norihiro KOMIYAMA, Seiji NOGUCHI, Yoshihiro IKURA, Yosuke SAKURAI, Yuichi HARADA
  • Patent number: 11631665
    Abstract: Provided is a semiconductor device comprising a semiconductor substrate that includes a transistor region; an emitter electrode that is provided on the semiconductor substrate; a first dummy trench portion that is provided on the transistor region of the semiconductor substrate and includes a dummy conducting portion that is electrically connected to the emitter electrode; and a first contact portion that is a partial region of the transistor region, provided between an end portion of a long portion of the first dummy trench portion and an end portion of the semiconductor substrate, and electrically connects the emitter electrode and a semiconductor region with a first conductivity type provided in the transistor region.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: April 18, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yuichi Harada
  • Publication number: 20230038712
    Abstract: Provided is a semiconductor device including: a semiconductor substrate having a drift region of a first conductivity type; and a buffer region of the first conductivity type provided between the drift region and a lower surface of the semiconductor substrate and having a higher doping concentration than the drift region. The buffer region has two or more helium chemical concentration peaks arranged at different positions in a depth direction of the semiconductor substrate.
    Type: Application
    Filed: October 23, 2022
    Publication date: February 9, 2023
    Inventors: Yuichi HARADA, Seiji NOGUCHI, Norihiro KOMIYAMA, Yoshihiro IKURA, Yosuke SAKURAI, Yoshihisa SUZUKI
  • Publication number: 20220328664
    Abstract: Provided is a semiconductor device that includes a first conductivity type well region below a gate runner portion, wherein a diode region includes first contact portions, a first conductivity type anode region, and a second conductivity type cathode region; wherein the well region contacts the diode region in the first direction, and when an end of the well region, an end of at least one of first contact portions, and an end of the cathode region that face one another in the first direction are imaginary projected on an upper surface of the semiconductor substrate, a first distance is longer than a second distance, the first distance being a distance between the end of the well region and the end of the cathode region, and the second distance being a distance between the end of the well region and the end of the at least one first contact portion.
    Type: Application
    Filed: June 23, 2022
    Publication date: October 13, 2022
    Inventors: Misaki TAKAHASHI, Yuichi HARADA, Kouta YOKOYAMA
  • Patent number: 11456359
    Abstract: A semiconductor device, including a substrate, and a deposit layer and a semiconductor layer formed sequentially on the substrate. The semiconductor layer has selectively disposed therein a first region, a second region and a contact region. A gate electrode is disposed on the first region and the semiconductor layer via a gate insulating film. A source electrode is formed in contact with the contact region and the second region. A drain electrode is disposed on the back surface of the substrate. The source electrode has a first titanium (Ti) film, and a titanium nitride (TiN) film, a second Ti film, and a metal film containing aluminum (Al) sequentially formed on the first Ti film. The source electrode may further include another TiN film, on which the first Ti film is formed.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: September 27, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasuyuki Hoshi, Yuichi Harada, Takashi Shiigi
  • Publication number: 20220277959
    Abstract: A semiconductor device comprising a semiconductor substrate including an upper surface and a lower surface wherein a donor concentration of a drift region is higher than a base doping concentration of the semiconductor substrate, entirely over the drift region in a depth direction connecting the upper surface and the lower surface is provided.
    Type: Application
    Filed: May 18, 2022
    Publication date: September 1, 2022
    Inventors: Yasunori AGATA, Takashi YOSHIMURA, Hiroshi TAKISHITA, Misaki MEGURO, Naoko KODAMA, Yoshihiro IKURA, Seiji NOGUCHI, Yuichi HARADA, Yosuke SAKURAI
  • Publication number: 20220216314
    Abstract: There is provided a semiconductor device including: a drift region of a first conductivity type disposed in a semiconductor substrate; a base region of a second conductivity type disposed above the drift region; an emitter region of the first conductivity type disposed above the base region; a plurality of trench portions arrayed in a predetermined array direction on a front surface side of the semiconductor substrate; a trench contact disposed on the front surface side of the semiconductor substrate between two adjacent trench portions; and a contact layer of the second conductivity type disposed under the trench contact and having a higher doping concentration than the base region, wherein a lower end of the trench contact is deeper than a lower end of the emitter region, and the emitter region and the contact layer are in contact with each other at a side wall of the trench contact.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 7, 2022
    Inventors: Yuichi HARADA, Seiji NOGUCHI, Norihiro KOMIYAMA, Yoshihiro IKURA, Yosuke SAKURAI
  • Patent number: 11380784
    Abstract: Provided is a semiconductor device that includes a first conductivity type well region below a gate runner portion, wherein a diode region includes first contact portions, a first conductivity type anode region, and a second conductivity type cathode region; wherein the well region contacts the diode region in the first direction, and when an end of the well region, an end of at least one of first contact portions, and an end of the cathode region that face one another in the first direction are imaginary projected on an upper surface of the semiconductor substrate, a first distance is longer than a second distance, the first distance being a distance between the end of the well region and the end of the cathode region, and the second distance being a distance between the end of the well region and the end of the at least one first contact portion.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: July 5, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Misaki Takahashi, Yuichi Harada, Kouta Yokoyama
  • Patent number: 11342186
    Abstract: A semiconductor device wherein a hydrogen concentration distribution has a first hydrogen concentration peak and a second hydrogen concentration peak and a donor concentration distribution has a first donor concentration peak and a second donor concentration peak in a depth direction, wherein the first hydrogen concentration peak and the first donor concentration peak are placed at a first depth and the second hydrogen concentration peak and the second donor concentration peak are placed at a second depth deeper than the first depth relative to the lower surface is provided.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: May 24, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasunori Agata, Takashi Yoshimura, Hiroshi Takishita, Misaki Meguro, Naoko Kodama, Yoshihiro Ikura, Seiji Noguchi, Yuichi Harada, Yosuke Sakurai
  • Publication number: 20220045047
    Abstract: Provided is a semiconductor device comprising a semiconductor substrate that includes a transistor region; an emitter electrode that is provided on the semiconductor substrate; a first dummy trench portion that is provided on the transistor region of the semiconductor substrate and includes a dummy conducting portion that is electrically connected to the emitter electrode; and a first contact portion that is a partial region of the transistor region, provided between an end portion of a long portion of the first dummy trench portion and an end portion of the semiconductor substrate, and electrically connects the emitter electrode and a semiconductor region with a first conductivity type provided in the transistor region.
    Type: Application
    Filed: October 25, 2021
    Publication date: February 10, 2022
    Inventor: Yuichi HARADA
  • Patent number: 11239356
    Abstract: A semiconductor device includes an N-type silicon carbide layer, a P-type region, an N-type source region, a P-type contact region, a gate insulating film, a gate electrode, and a source electrode on the front surface side of an N-type silicon carbide substrate. A drain electrode is located on the back surface of the N-type silicon carbide substrate. A life time killer introduction region is located along an entire interface of the N-type silicon carbide layer and the bottom face of the P-type region. The life time killer is introduced by implanting helium or protons from the back surface side of the N-type silicon carbide substrate after forming a surface structure of an element on the front surface side of the N-type silicon carbide substrate and before forming the drain electrode.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: February 1, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akimasa Kinoshita, Yasuyuki Hoshi, Yuichi Harada, Yasuhiko Oonishi
  • Patent number: 11158631
    Abstract: Provided is a semiconductor device comprising a semiconductor substrate that includes a transistor region; an emitter electrode that is provided on the semiconductor substrate; a first dummy trench portion that is provided on the transistor region of the semiconductor substrate and includes a dummy conducting portion that is electrically connected to the emitter electrode; and a first contact portion that is a partial region of the transistor region, provided between an end portion of a long portion of the first dummy trench portion and an end portion of the semiconductor substrate, and electrically connects the emitter electrode and a semiconductor region with a first conductivity type provided in the transistor region.
    Type: Grant
    Filed: October 27, 2019
    Date of Patent: October 26, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yuichi Harada
  • Publication number: 20210320195
    Abstract: Provided is a semiconductor device that has a plurality of gate trench portions electrically connected to a gate electrode, and a plurality of dummy trench portions electrically connected to an emitter electrode, and includes a first trench group that includes one gate trench portion and two dummy trench portions adjacent to the gate trench portion and adjacent to each other, and a second trench group that includes two gate trench portions adjacent to each other.
    Type: Application
    Filed: June 24, 2021
    Publication date: October 14, 2021
    Inventors: Yuichi HARADA, Seiji NOGUCHI, Norihiro KOMIYAMA, Yoshihiro IKURA, Yosuke SAKURAI
  • Patent number: 11107910
    Abstract: Provided is a semiconductor device that includes: a first conductivity type anode region provided in the semiconductor substrate in the diode region; a second conductivity type drift region that is located below the anode region in the semiconductor substrate; a second conductivity type accumulation region that is located between the anode region and the drift region in a depth direction of the semiconductor substrate; and an insulating film that includes a plurality of contact portions extending in a first direction and is provided on an upper surface of the semiconductor substrate; wherein the plurality of contact portions include a first contact portion provided in the diode region; and the first contact portion includes a first non-overlapping region in which an end of the first contact portion and the accumulation region in the first direction do not overlap in the depth direction.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: August 31, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi Harada, Misaki Takahashi, Kouta Yokoyama