Patents by Inventor Yuichi HASHIZUME

Yuichi HASHIZUME has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10347735
    Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a gate insulating film, and a gate electrode. The semiconductor device further includes, in a region of the first semiconductor layer across or adjacent to a p-n junction therein that does not overlap the second semiconductor region in a plan view except lateral edges thereof, a lifetime killer region having lifetime killers implanted therein.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: July 9, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Keishirou Kumada, Yuichi Hashizume, Yasuyuki Hoshi
  • Publication number: 20190131443
    Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a gate electrode, a first electrode, and a gate electrode pad. A first lower region opposing the gate electrode pad in a depth direction has a carrier recombination rate that is lower than that of a second lower region opposing the first electrode in the depth direction. With such a configuration, when high electric potential is applied to a source electrode and a built-in PN diode is driven, the generation of crystal defects may be suppressed.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yasuyuki HOSHI, Keishirou KUMADA, Yuichi HASHIZUME
  • Publication number: 20190131444
    Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the first conductivity type, a gate insulating film, and a gate electrode. A threshold voltage of the semiconductor device is higher than forward voltage of a built-in PN diode constituted by the second semiconductor layer, the semiconductor substrate, and the first semiconductor layer. Thus, when high electric potential is applied to a source electrode and the built-in PN diode is driven, the generation of crystal effects may be suppressed.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi HASHIZUME, Keishirou KUMADA, Yasuyuki HOSHI
  • Publication number: 20190109065
    Abstract: An interlayer insulating film covers a gate electrode and a gate insulating film embedded in a trench. A source electrode includes a first TiN film, a NiSi film, a Ti film, a second TiN film, and an Al alloy film. The first TiN film covers a part of the interlayer insulating film so as to not contact a semiconductor substrate at a bottom of a contact hole. The NiSi film forms an ohmic contact with the semiconductor substrate in the contact hole. The Ti film, the second TiN film, and the Al alloy film are sequentially stacked on surfaces of the first TiN film and the NiSi film, spanning a front surface of the semiconductor substrate, from on the interlayer insulating film. A terminal pin is soldered to the source electrode 16, in an upright position orthogonal to the front surface of the semiconductor substrate.
    Type: Application
    Filed: August 27, 2018
    Publication date: April 11, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi HASHIZUME, Keishirou KUMADA, Yoshihisa SUZUKI, Yasuyuki HOSHI
  • Publication number: 20190074359
    Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type provided on a front surface of a semiconductor substrate of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; and a gate electrode having a striped-shape and provided on a gate insulating film. The silicon carbide semiconductor device further includes a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region; a step film provided on the first electrode; a plating film provided on the first electrode and the step film; and a solder on the plating film. The step film is provided on the first electrode on which the solder and the plating film are provided, the step film being provided so as to be embedded in grooves formed on the first electrode.
    Type: Application
    Filed: July 31, 2018
    Publication date: March 7, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi Hashizume, Keishirou Kumada, Yasuyuki Hoshi
  • Publication number: 20190043957
    Abstract: A silicon carbide semiconductor device includes a semiconductor substrate of a first conductivity type; an active region in which a main current flows provided on the semiconductor substrate; a termination region disposed outside of the active region and in which a voltage withstanding structure is formed; and a damaged region disposed outside the termination region and in which crystallinity is impaired, the damaged region being exposed at a cut surface that is formed when singulation is performed.
    Type: Application
    Filed: June 28, 2018
    Publication date: February 7, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yasuyuki HOSHI, Yuichi HASHIZUME, Keishirou KUMADA
  • Publication number: 20180233564
    Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a gate insulating film, and a gate electrode. The semiconductor device further includes, in a region of the first semiconductor layer across or adjacent to a p-n junction therein that does not overlap the second semiconductor region in a plan view except lateral edges thereof, a lifetime killer region having lifetime killers implanted therein.
    Type: Application
    Filed: January 5, 2018
    Publication date: August 16, 2018
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Keishirou KUMADA, Yuichi HASHIZUME, Yasuyuki HOSHI
  • Patent number: 9070400
    Abstract: A method of manufacturing a magnetic recording medium includes providing a substrate that is a magnetic recording medium substrate having a disc shape, having two main surfaces, and having defined therein a center hole; holding the center hole of the substrate from both main surfaces with two holding members that each have a disc shape to hold the substrate and to cover at least the periphery of the center hole adjacent to the two main surfaces of the substrate; and applying resist liquid simultaneously to both main surfaces of the substrate using spin coating to form a resist layer simultaneously on both main surfaces while maintaining the periphery of the center hole immediately adjacent to the two main surfaces of the substrate resist-free as an unapplied portion. The method enables efficient formation of uniform resist layers without defects on both faces of the substrate.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: June 30, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi Hashizume, Kunio Hibino
  • Publication number: 20100330270
    Abstract: A method of manufacturing a magnetic recording medium includes providing a substrate that is a magnetic recording medium substrate having a disc shape, having two main surfaces, and having defined therein a center hole; holding the center hole of the substrate from both main surfaces with two holding members that each have a disc shape to hold the substrate and to cover at least the periphery of the center hole adjacent to the two main surfaces of the substrate; and applying resist liquid simultaneously to both main surfaces of the substrate using spin coating to form a resist layer simultaneously on both main surfaces while maintaining the periphery of the center hole immediately adjacent to the two main surfaces of the substrate resist-free as an unapplied portion. The method enables efficient formation of uniform resist layers without defects on both faces of the substrate.
    Type: Application
    Filed: June 22, 2010
    Publication date: December 30, 2010
    Applicant: Fuji Electric Device Technology Co., Ltd.
    Inventors: Yuichi HASHIZUME, Kunio Hibino