Abstract: The present technology relates to a data processing apparatus and a data processing method that are able to secure good communication quality in data transmission using an LDPC code. One symbol is mapped to one of 16 signal points prescribed in 16APSK, with code bits of four bits of an LDPC code having a code length of 16200 bits and a code rate of 7/15 as one symbol. 16 signal points prescribed in 16APSK are four signal points on an inner circle and 12 signal points on an outer circle, and a radius ratio of the inner circle and the outer circle is 5.25. The present technology may be applied to, for example, a case of performing data transmission using an LDPC code.

Abstract: The present technology relates to a reception apparatus and a data processing method that permit efficient processing of time information. The reception apparatus receives a digital broadcasting signal based on an IP transport scheme, acquires time information from a physical layer frame transported in a physical layer of a protocol stack for the IP transport scheme, converts the acquired time information into the same data format as data provided in a payload of the physical layer frame, and outputs the converted time information to a processing section that performs a given process relating to an upper layer that is a layer higher than the physical layer. The present technology is applicable, for example, to a television receiver that supports an IP transport scheme.

Abstract: A method of manufacturing a laminated core includes inserting permanent magnets 14 into magnet insertion holes 12, 12a of a core body 13; injecting a resin 18 into the holes 12, 12a from resin reservoir pots 17 in the die 15 (16) to fix the magnets 14; placing a dummy plate 19 between the die 15 having the pots 17 and the body 13, the plate 19 having gate holes 35, 35a guiding the resin 18 from the pots 17 into the holes 12, 12a, the hole 35 (35a) overlapping with both of a part of the hole 12 (12a) and a surface of the body 13; poring the resin 18 via the holes 35, 35a and curing the resin 18 in the holes 12, 12a; and separating the plate 19 from the body 13 to remove the resin 18 overflowed from the holes 12, 12a.

Abstract: Communication reception that enables reception of a packet which may not contain an error without invalidating the same is disclosed. In one example, an information analyzing unit analyzes a data string and frame/slot information, and supplies TMCC information, slot header information, and data length information to a packet length indicating unit and a packet dividing unit. The packet length indicating unit defines the packet length in advance, and indicates the defined packet length to the packet dividing unit. The packet dividing unit performs packet division on the basis of the packet length obtained from the TMCC information, the slot header information, the data length information and the like from the information analyzing unit, and the packet length defined by the packet length indicating unit.

Abstract: The present technology relates to a reception device, a receiving method, and a program capable of improving a reception 6state. A delay wave by multipath is estimated on the basis of sensor information detected by a sensor unit, a replica of the delay wave is generated by a sum of products of a coefficient for each delay wave and a signal of a reception wave according to delay time on the basis of the estimated delay wave by the multipath, and the generated replica of the delay wave is subtracted from the signal of the reception wave, thereby removing the delay wave from the signal of the reception wave. The present technology may be applied to a receiver which receives a broadcast wave.

Abstract: The present technology relates to a signal processing device, a signal processing method, and a program that enable transmission of time information in TLVs. The signal processing device includes: a demodulation processing unit that performs a demodulation process; and a processing unit that performs a demux process. In the signal processing device, time information included in a variable-length packet is transmitted from the demodulation processing unit to the processing unit at regular intervals. The variable-length packet is a Type Length Value (TLV) packet. The time information is Network Time Protocol (NTP) included in the TLV packet. The time information is placed at a predetermined position in a TLV stream including the TLV packet. The present technology can be applied to receivers that receive and process TLV streams.

Abstract: The present technology relates to a signal processing device that enables TLV transmission, a signal processing method, and a program. The signal processing device includes: a demodulation processing unit that performs a demodulation process; a processing unit that performs a demux process; and a data signal line, a clock signal line, a sync signal line, and a valid signal line that are provided between the demodulation processing unit and the processing unit. A variable-length packet is transmitted between the demodulation processing unit and the processing unit through the data signal line, the clock signal line, the sync signal line, and the valid signal line. The variable-length packet is an Internet Protocol (IP) packet. The present technology can be applied to receivers that receive and process TLV streams.

Abstract: The present technology relates to a reception apparatus and a data processing method that permit efficient processing of time information. The reception apparatus receives a digital broadcasting signal based on an IP transport scheme, acquires time information from a physical layer frame transported in a physical layer of a protocol stack for the IP transport scheme, converts the acquired time information into the same data format as data provided in a payload of the physical layer frame, and outputs the converted time information to a processing section that performs a given process relating to an upper layer that is a layer higher than the physical layer. The present technology is applicable, for example, to a television receiver that supports an IP transport scheme.

Abstract: The present technology relates to a reception apparatus and a data processing method that enable clock synchronization in a more suitable manner. The reception apparatus receives a digital broadcast signal of an IP transmission method that includes time information and a stream of content. The time information includes a seconds field and a nanoseconds field. The reception apparatus then generates a processing clock synchronized with the time information on the basis of the time information included in the digital broadcast signal, and processes the stream included in the digital broadcast signal on the basis of the processing clock. The present technology can be applied to, for example, television receivers conforming to the IP transmission method.

Abstract: There is provided a signal processing device including a selection unit that selects and outputs one clock serving as a transport stream (TS) clock, which represents timing of data of a TS, among a plurality of clocks with frequencies not less than a serial rate which is a data rate at which the TS included in a radio frequency (RF) signal is output in a serial manner.

Abstract: A code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 is interchanged with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK. In the interchanging, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i +1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i, a (#i +1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, and a bit b0, a bit b1, and a bit b2 are interchanged with a bit y1, a bit y0, and a bit y2.

Abstract: The present technology relates to a data processing apparatus and a data processing method that are able to secure good communication quality in data transmission using an LDPC code. One symbol is mapped to one of 16 signal points prescribed in 16APSK, with code bits of four bits of an LDPC code having a code length of 16200 bits and a code rate of 7/15 as one symbol. 16 signal points prescribed in 16APSK are four signal points on an inner circle and 12 signal points on an outer circle, and a radius ratio of the inner circle and the outer circle is 5.25. The present technology may be applied to, for example, a case of performing data transmission using an LDPC code.

Abstract: A code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15 is interchanged with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK. When 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, and a bit b0 is interchanged with a bit y1, a bit b1 is interchanged with a bit y0, and a bit b2 is interchanged with a bit y2.

Abstract: In a transmitting device, in interchanging to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a bit b0, a bit b1, and a bit b2 are interchanged with a bit y1, a bit y0, and a bit y2, respectively. A position of the interchanged code bit obtained from data transmitted from the transmitting device is returned to an original position. The present technology is applicable to a case of transmitting data using an LDPC code, for example.

Abstract: In a transmitting device, in interchanging to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a bit b0, a bit b1, and a bit b2 are interchanged with a bit y1, a bit y0, and a bit y2, respectively. A position of the interchanged code bit obtained from data transmitted from the transmitting device is returned to an original position. The present technology is applicable to a case of transmitting data using an LDPC code, for example.

Abstract: Provided is a signal processing device including: a valid clock width calculation unit configured to calculate a valid clock width corresponding to a bit rate of a valid section in which a transport stream (TS) packet exists; and a TS clock signal generation unit configured to generate, on a basis of the valid clock width calculated by the valid clock width calculation unit, a TS clock signal by combining clocks with different frequency dividing rates.

Abstract: A method of manufacturing a laminated core includes inserting permanent magnets 14 into magnet insertion holes 12, 12a of a core body 13; injecting a resin 18 into the holes 12, 12a from resin reservoir pots 17 in the die 15 (16) to fix the magnets 14; placing a dummy plate 19 between the die 15 having the pots 17 and the body 13, the plate 19 having gate holes 35, 35a guiding the resin 18 from the pots 17 into the holes 12, 12a, the hole 35 (35a) overlapping with both of a part of the hole 12 (12a) and a surface of the body 13; poring the resin 18 via the holes 35, 35a and curing the resin 18 in the holes 12, 12a; and separating the plate 19 from the body 13 to remove the resin 18 overflowed from the holes 12, 12a.

Abstract: A method of manufacturing a laminated core includes inserting permanent magnets 14 into magnet insertion holes 12, 12a of a core body 13; injecting a resin 18 into the holes 12, 12a from resin reservoir pots 17 in the die 15 (16) to fix the magnets 14; placing a dummy plate 19 between the die 15 having the pots 17 and the body 13, the plate 19 having gate holes 35, 35a guiding the resin 18 from the pots 17 into the holes 12, 12a, the hole 35 (35a) overlapping with both of a part of the hole 12 (12a) and a surface of the body 13; poring the resin 18 via the holes 35, 35a and curing the resin 18 in the holes 12, 12a; and separating the plate 19 from the body 13 to remove the resin 18 overflowed from the holes 12, 12a.

Abstract: The present technique relates to a demodulation device, a demodulation method and a program capable of realizing a demodulation process at a rate equivalent to a case where I and Q channel signals are not inverted, even when the I and Q channel signals are inverted. A frequency correction unit establishes synchronization of a frequency and clock based on a signal from a frequency synchronization unit. A channel inversion detection unit of a frame synchronization unit detects presence or absence of inversion of I and Q channel signals, and supplies, as a detection result, a channel inversion detection result to the channel inversion control unit. The channel inversion control unit switches the I and Q channel signals if the inversion has occurred, based on the channel inversion detection result. This technique can be applied to a demodulation device.

Abstract: A code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15 is interchanged with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK. When 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, and a bit b0 is interchanged with a bit y1, a bit b1 is interchanged with a bit y0, and a bit b2 is interchanged with a bit y2.