Patents by Inventor Yuichi Hirofuji
Yuichi Hirofuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8395194Abstract: A solid-state imaging device according to the present invention is of a MOS type and includes a plurality of pixels arranged in rows and columns, and includes: a semiconductor substrate; a photodiode which is formed in the semiconductor substrate and converts, into a signal charge, light that is incident from a first main surface of the semiconductor substrate; a transfer transistor which is formed in a second main surface of the semiconductor substrate and transfers the signal charge converted by the photodiode; a light shielding film which is conductive and formed on a boundary between the pixels, above the first main surface of the semiconductor substrate; an overflow drain region electrically connected to the light shielding film and formed in the first main surface of the semiconductor substrate; and an overflow barrier region formed between the overflow drain region and the photodiode.Type: GrantFiled: September 21, 2011Date of Patent: March 12, 2013Assignee: Panasonic CorporationInventors: Haruhisa Yokoyama, Hiroshi Sakoh, Kazuhiro Yamashita, Mitsuo Yasuhira, Yuichi Hirofuji
-
Publication number: 20120146156Abstract: A semiconductor device includes an MIS transistor and an electric fuse. The MIS transistor includes a gate insulating film formed on the semiconductor substrate, and a gate electrode including a first polysilicon layer, a first silicide layer, and a first metal containing layer made of a metal or a conductive metallic compound. The electric fuse includes an insulating film formed on the semiconductor substrate, a second polysilicon layer formed over the insulating film, and a second silicide layer formed on the second polysilicon layer.Type: ApplicationFiled: February 15, 2012Publication date: June 14, 2012Applicant: PANASONIC CORPORATIONInventors: MASANORI SHIRAHAMA, YASUHIRO AGATA, TOSHIAKI KAWASAKI, YUICHI HIROFUJI, TAKAYUKI YAMADA
-
Publication number: 20120037960Abstract: A solid-state imaging device according to the present invention is of a MOS type and includes a plurality of pixels arranged in rows and columns, and includes: a semiconductor substrate; a photodiode which is formed in the semiconductor substrate and converts, into a signal charge, light that is incident from a first main surface of the semiconductor substrate; a transfer transistor which is formed in a second main surface of the semiconductor substrate and transfers the signal charge converted by the photodiode; a light shielding film which is conductive and formed on a boundary between the pixels, above the first main surface of the semiconductor substrate; an overflow drain region electrically connected to the light shielding film and formed in the first main surface of the semiconductor substrate; and an overflow barrier region formed between the overflow drain region and the photodiode.Type: ApplicationFiled: September 21, 2011Publication date: February 16, 2012Applicant: PANASONIC CORPORATIONInventors: Haruhisa YOKOYAMA, Hiroshi SAKOH, Kazuhiro YAMASHITA, Mitsuo YASUHIRA, Yuichi HIROFUJI
-
Patent number: 7978043Abstract: A semiconductor device includes a semiconductor substrate including at least one of a circuit and a circuit element, and an inductor element having a coil axis extending in a direction parallel to a main surface of the semiconductor substrate and disposed adjacent to the main surface. A main direction of a magnetic field induced by passing a current through the inductor element is parallel to the main surface.Type: GrantFiled: July 29, 2010Date of Patent: July 12, 2011Assignee: Panasonic CorporationInventors: Yutaka Nabeshima, Yuichi Hirofuji
-
Publication number: 20100289608Abstract: A semiconductor device includes a semiconductor substrate including at least one of a circuit and a circuit element, and an inductor element having a coil axis extending in a direction parallel to a main surface of the semiconductor substrate and disposed adjacent to the main surface. A main direction of a magnetic field induced by passing a current through the inductor element is parallel to the main surface.Type: ApplicationFiled: July 29, 2010Publication date: November 18, 2010Applicant: PANASONIC CORPORATIONInventors: Yutaka NABESHIMA, Yuichi HIROFUJI
-
Publication number: 20070205488Abstract: A light-detecting device, comprising: a semiconductor substrate 101 that is composed of silicon as a base material, and contains carbon at a predetermined concentration; and an epitaxial layer 102 that is formed on the semiconductor substrate 101 and composed of silicon as a base material, the epitaxial layer 102 including a light-detecting unit (mainly 104) a predetermined distance away from the semiconductor substrate 101, wherein the semiconductor substrate 101 is formed using a crystal growth method from melt obtained by melting a material containing silicon and a material containing carbon so that carbon is contained in the semiconductor substrate 101 at the predetermined concentration.Type: ApplicationFiled: March 2, 2007Publication date: September 6, 2007Inventors: Jun Hirai, Masakatsu Suzuki, Ichiro Murakami, Yuichi Hirofuji
-
Patent number: 5856219Abstract: The invention relates to a high-density DRAM fabrication technique for forming a source/drain contact between word lines in a self-alignment manner, with the offset length between a source region and a drain region of a peripheral transistor maintained at an adequate value. After gate electrodes (i.e. word lines) are formed, a first insulating layer, which is thin enough not to block up space defined between the word lines, is deposited. The source/drain contact is etched as deep as the first insulating layer is thick to form an extraction electrode made of polycrystalline silicon. A second insulating layer is deposited until a spacer thickness (i.e. the sum of the film thickness of the second insulating layer and the film thickness of the first insulating layer) for determining the offset length is obtained.Type: GrantFiled: August 18, 1997Date of Patent: January 5, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasushi Naito, Yutaka Ito, Yuichi Hirofuji
-
Patent number: 5472906Abstract: A first underlaid oxide layer, a polysilicon layer, and a first silicon nitride layer are formed on a silicon substrate in this order. Using a photoresist as a mask, a portion of the first silicon nitride layer, the polysilicon layer, the first underlaid oxide layer and the silicon substrate which is to be an isolation region is etched by a depth which regulates a length of bird's beak and a threshold voltage drop of a FET adequately. After forming a second underlaid oxide layer and a second silicon nitride layer, silicon nitride side walls of more than 25 nm in thickness are formed. An isolation oxide layer is formed by selective oxidation, using the silicon nitride layer as a mask. Favorable etched depth in the step of removing the silicon substrate is one third of the thickness of the isolation oxide layer. Favorable etched depth in case of a normal FET is 20-100 nm.Type: GrantFiled: August 18, 1994Date of Patent: December 5, 1995Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Norisato Shimizu, Yasushi Naito, Yuichi Hirofuji
-
Patent number: 5422013Abstract: A flow passage into which water-to-be-treated flows is provided with, in order from an upstream side, a deaerator as a DO eliminating device having a power variable mechanism, an oxidation device for oxidizing TOC by irradiating ultraviolet-ray, an ion eliminating device for eliminating TOC ion generated at oxidation, and a particle eliminating device. Further provided thereat are a TOC density measuring device, a DO density measuring device and a data processing device. Before the water-to-be-treated is irradiated with ultraviolet-ray in the TOC eliminating device (oxidation device and ion eliminating device), the deaerator controls a DO density in the water-to-be-treated according to a TOC density. Thus, an oxidizer of the TOC is maintained and impurity is decreased.Type: GrantFiled: May 14, 1993Date of Patent: June 6, 1995Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Yuichi Hirofuji
-
Patent number: 5092937Abstract: Semiconductors are treated with such surface-treating solutions as ultra-pure water, dilute hydrofluoric acid and an organic solvent and then subjected to removal of the surface-treating solutions remaining on the surface of the semiconductor in an inert gas atmosphere of high purity while contacting the surface of the surface-treated semiconductor only with the inert gas of high purity, whereby contamination with impurities on atom level from the atmosphere can be prevented.Type: GrantFiled: July 13, 1990Date of Patent: March 3, 1992Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mototsugu Ogura, Keiichi Kagawa, Yuichi Hirofuji
-
Patent number: 4459496Abstract: In a stacked, multilayer IIL (integrated injection logic) circuit, with which power consumption can be significantly reduced, a discharging circuit constructed of an IIL constant-current circuit or of a resistor is provided for one of transistors which are used for shifting the level of a signal from an IIL circuit of a top layer to an IIL circuit of a bottom layer, so that signal transmission therebetween is prevented from deterioration. A charging circuit may be added to another transistor, while a diode may be interposed between these transistors. Additional diodes may be interposed between adjacent layers for speeding up the signal transmission from one layer to another upper layer.Type: GrantFiled: April 3, 1981Date of Patent: July 10, 1984Assignee: Matsushita Electric Industrial Company, LimitedInventors: Haruyasu Yamada, Toyoki Takemoto, Tadao Komeda, Tsutomu Fujita, Yuichi Hirofuji, Hiroyuki Sakai