Abstract: Disclosed herein is a peripheral equipment control device controlling data flow via a peripheral equipment, the peripheral equipment control device including: a peripheral equipment control processor that can control an operation of one or more peripheral equipment; and a bus adapted to connect the peripheral equipment control processor, a main processor, and the one or more peripheral equipment, the main processor being provided outside the peripheral equipment control device to control the operation of the one or more peripheral equipment, in which the bus stores addresses that are referenced by the main processor and the peripheral equipment control processor to access the one or more peripheral equipment, and the bus prohibits access to the peripheral equipment by the peripheral equipment control processor while the main processor is active.

Abstract: Disclosed herein is a peripheral equipment control device controlling data flow via a peripheral equipment, the peripheral equipment control device including: a peripheral equipment control processor that can control an operation of one or more peripheral equipment; and a bus adapted to connect the peripheral equipment control processor, a main processor, and the one or more peripheral equipment, the main processor being provided outside the peripheral equipment control device to control the operation of the one or more peripheral equipment, in which the bus stores addresses that are referenced by the main processor and the peripheral equipment control processor to access the one or more peripheral equipment, and the bus prohibits access to the peripheral equipment by the peripheral equipment control processor while the main processor is active.

Abstract: There is disclosed an interface device which can prevent the freezing of an information processing system caused occupation of a system bus even when a wait signal outputted from the PC card is kept asserted. When the wait signal outputted from the PC card, is asserted, a timer portion 201 is activated. When the timer portion 201 detects that the wait signal is kept asserted for more than a predetermined period of time, it asserts a wait mask signal. Upon assertion of the wait mask signal, a mask portion 202 masks the wait signal from the PC card so that the wait signal to the CPU is negated even when the wait signal is kept asserted. Further, when the timer portion 201 asserts the wait mask signal, an interrupt control block/card status register 210 asserts an interrupt signal to the CPU.

Abstract: An entertainment apparatus comprising a peripheral device and a controller for controlling the peripheral device. The peripheral device and the controller are connected each other by an address bus and a data bus. The peripheral device which receives a DMA acknowledge signal from the controller carries out 32-bit DMA transfer using lower 16 bits of the address bus and the data bus, during assertion of the DMA acknowledge signal.

Abstract: An entertainment apparatus comprising a peripheral device and a controller for controlling the peripheral device. The peripheral device and the controller are connected each other by an address bus and a data bus. The peripheral device which receives a DMA acknowledge signal from the controller carries out 32-bit DMA transfer using lower 16 bits of the address bus and the data bus, during assertion of the DMA acknowledge signal.

Abstract: There is disclosed an interface device which can prevent the freezing of an information processing system caused occupation of a system bus even when a wait signal outputted from the PC card is kept asserted. When the wait signal outputted from the PC card, is asserted, a timer portion 201 is activated. When the timer portion 201 detects that the wait signal is kept asserted for more than a predetermined period of time, it asserts a wait mask signal. Upon assertion of the wait mask signal, a mask portion 202 masks the wait signal from the PC card so that the wait signal to the CPU is negated even when the wait signal is kept asserted. Further, when the timer portion 201 asserts the wait mask signal, an interrupt control block/card status register 210 asserts an interrupt signal to the CPU.

Abstract: The pin definition of a PC card having a plurality of specification modes is changed stepwise in a state that it is mounted in a PC card slot. This realizes mode switching in an active state while preventing the pin functions of the PC card 10 and the PC card slot 20 from conflicting with each other. A standardized mode is employed when the PC card 10 is in the initial state. Information to the effect that the PC card is mode-switchable is written to a special area of the PC card 10 in advance. This makes it possible to use the PC card for general purposes.

Abstract: A recording and/or reproducing apparatus for recording and/or reproducing digital audio signal on a recording medium such as a magnetic tape, which includes a recording and/or reproducing unit, an analog-to-digital convertor, a decimation filter, and noise shaper. The recording and/or reproducing unit records and/or reproduces signal on a recording medium at a speed double relative moving speed of a head and the recording medium at least. The analog-to-digital convertor converts input analog audio signal into digital signal with a sampling frequency which is above the audio frequency band, and sufficiently higher than the maximum frequency capable of recording by the recording and/or reproducing unit. The decimation filter reduces the sampling frequency of the digital signal output from the analog-to-digital convertor, and converts it into digital signal of m-bit (m>n).

Abstract: A recording and/or reproducing apparatus for recording and/or reproducing digital audio signal on a recording medium such as a magnetic tape, which includes a recording and/or reproducing unit, an analog-to-digital convertor, a decimation filter, and noise shaper. The recording and/or reproducing unit records and/or reproduces signal on a recording medium at a speed double relative moving speed of a head and the recording medium at least. The analog-to-digital convertor converts input analog audio signal into digital signal with a sampling frequency which is above the audio frequency band, and sufficiently higher than the maximum frequency capable of recording by the recording and/or reproducing unit. The decimation filter reduces the sampling frequency of the digital signal output from the analog-to-digital convertor, and converts it into digital signal of m-bit (m>n).

Abstract: A quantization apparatus for quantizing and word length limiting digitized stereo input signals including a stereo dither signal generating unit for generating stereo dither signals synthesized from at least two distinct dither signals not correlated to each other at an arbitrary ratio, a first addition unit for adding one of the stereo dither signals to one of the digital stereo input signals, a second addition unit for adding the other of the stereo dither signals to the other of the digital stereo input signals, a first quantization unit for quantizing and word length limiting an output signal of the first addition unit, and a second quantization unit for quantizing and word length limiting an output signal of the second addition unit. With the present quantization device, the stereo input signals may be quantized while cross-correlation between the left and right channel stereo input signals is maintained.