Abstract: A method can include, in a default mode of a memory device, decoding command data received on a unidirectional command address (CA) bus of a memory interface according to a first standard. In response to decoding a mode enter command, placing the memory device into an alternate management mode. In the alternate management mode, receiving alternate command data on the CA bus, and in response to receiving a command execute indication on the CA bus, decoding alternate command data according to a second standard to execute an alternate command. In response to decoding a mode exit command received on the CA bus according to the first standard, returning the memory device to the default mode. The memory interface comprises the CA bus and a data bus, and the CA bus and data bus comprise a plurality of parallel input connections. Corresponding devices and systems are also disclosed.

Abstract: In an embodiment, a method includes: receiving, via control lines of a parallel interface of a memory device, a first command and a first read command including one or more bits indicative of a first selection that causes a selector circuit to select data from a data memory portion of the memory device; providing, via data lines of the parallel interface, first data from the data memory portion using the selector circuit, where the provided first data is associated with the first read command; receiving, via the control lines, a second command and a second read command including one or more bits indicative of a second selection that causes the selector circuit to select data from an ECC memory portion; and providing, via the data lines, first ECC values from the ECC memory portion using the selector circuit, where the first ECC values are associated with the first data.

Abstract: A method can include, in a default mode of a memory device, decoding command data received on a unidirectional command address (CA) bus of a memory interface according to a first standard. In response to decoding a mode enter command, placing the memory device into an alternate management mode. In the alternate management mode, receiving alternate command data on the CA bus, and in response to receiving a command execute indication on the CA bus, decoding alternate command data according to a second standard to execute an alternate command. In response to decoding a mode exit command received on the CA bus according to the first standard, returning the memory device to the default mode. The memory interface comprises the CA bus and a data bus, and the CA bus and data bus comprise a plurality of parallel input connections. Corresponding devices and systems are also disclosed.

Abstract: In an embodiment, a method includes: receiving, via control lines of a parallel interface of a memory device, a first command and a first read command including one or more bits indicative of a first selection that causes a selector circuit to select data from a data memory portion of the memory device; providing, via data lines of the parallel interface, first data from the data memory portion using the selector circuit, where the provided first data is associated with the first read command; receiving, via the control lines, a second command and a second read command including one or more bits indicative of a second selection that causes the selector circuit to select data from an ECC memory portion; and providing, via the data lines, first ECC values from the ECC memory portion using the selector circuit, where the first ECC values are associated with the first data.

Abstract: A method can include storing first instruction data in a first region of a nonvolatile memory device; mapping addresses of the first region to predetermined memory address spaces of a processor device; executing the first instruction data from the first region with the processor device; receiving second instruction data for the processor device. While the first instruction data remains available to the processor device, the second instruction data can be written into a second region of the nonvolatile memory device. By operation of the processor device, addresses of the second region can be remapped to the predetermined memory address spaces of the processor device; and executing the second instruction data from the second region with the processor device.

Abstract: Example apparatus, systems and methods receive a new firmware image at a memory device and place the new firmware image into second nonvolatile storage locations of the memory device such that the second nonvolatile storage locations do not overlap with first nonvolatile storage locations of the memory device that store a current firmware image. Embodiments place a logical address to physical address mapping for the new firmware image into a remap data structure stored in memory circuits of the memory device. The remap data structure also includes a logical address to physical address mapping for the current firmware image. Embodiments provide a first status value to indicate that the logical address to physical address mapping for the new firmware image is a valid firmware image and a second status value to indicate that the logical address to physical address mapping for the current firmware image is an invalid firmware image.

Abstract: A method can include storing first instruction data in a first region of a nonvolatile memory device; mapping addresses of the first region to predetermined memory address spaces of a processor device; executing the first instruction data from the first region with the processor device; receiving second instruction data for the processor device. While the first instruction data remains available to the processor device, the second instruction data can be written into a second region of the nonvolatile memory device. By operation of the processor device, addresses of the second region can be remapped to the predetermined memory address spaces of the processor device; and executing the second instruction data from the second region with the processor device.

Abstract: Example apparatus, systems and methods receive a new firmware image at a memory device and place the new firmware image into second nonvolatile storage locations of the memory device such that the second nonvolatile storage locations do not overlap with first nonvolatile storage locations of the memory device that store a current firmware image. Embodiments place a logical address to physical address mapping for the new firmware image into a remap data structure stored in memory circuits of the memory device. The remap data structure also includes a logical address to physical address mapping for the current firmware image. Embodiments provide a first status value to indicate that the logical address to physical address mapping for the new firmware image is a valid firmware image and a second status value to indicate that the logical address to physical address mapping for the current firmware image is an invalid firmware image.

Abstract: A memory device can include a memory cell array and a remap data structure. A remap data structure can include a mapping history section configured to store sets of mappings between logical addresses and the physical addresses of the regions, and a status section configured to identify one of the sets of mappings as a live set for the device. Control logic can be coupled to the memory cell array and the remap data structure and configured to enable access to the storage locations and remap data structure. Firmware update systems and methods, including firmware-over-the-air (FOTA), that include a memory device are also disclosed.

Abstract: Disclosed herein are system, method, and computer program product embodiments for accessing data of a memory. A method embodiment operates by receiving one or more requests for data stored across at least a first memory area and a second memory area of a memory. The method continues with performing, by at least one processor, a wrapped read of data within a first memory area of the memory. The method then performs, by the at least one processor, a continuous read of data within a second memory area of the memory, the second memory area being adjacent to the first memory area. The continuous read starts at a first boundary of the second memory area, and is performed automatically after the wrapped read of data within the first memory area.

Abstract: A memory device can include a memory cell array and a remap data structure. A remap data structure can include a mapping history section configured to store sets of mappings between logical addresses and the physical addresses of the regions, and a status section configured to identify one of the sets of mappings as a live set for the device. Control logic can be coupled to the memory cell array and the remap data structure and configured to enable access to the storage locations and remap data structure. Firmware update systems and methods, including firmware-over-the-air (FOTA), that include a memory device are also disclosed.

Abstract: Disclosed herein are system, method, and computer program product embodiments for accessing data of a memory. A method embodiment operates by receiving one or more requests for data stored across at least a first memory area and a second memory area of a memory. The method continues with performing, by at least one processor, a wrapped read of data within a first memory area of the memory. The method then performs, by the at least one processor, a continuous read of data within a second memory area of the memory, the second memory area being adjacent to the first memory area. The continuous read starts at a first boundary of the second memory area, and is performed automatically after the wrapped read of data within the first memory area.

Abstract: Disclosed herein are system, method, and computer program product embodiments for accessing data of a memory. A method embodiment operates by receiving one or more requests for data stored across at least a first memory area and a second memory area of a memory. The method continues with performing, by at least one processor, a wrapped read of data within a first memory area of the memory. The method then performs, by the at least one processor, a continuous read of data within a second memory area of the memory, the second memory area being adjacent to the first memory area. The continuous read starts at a first boundary of the second memory area, and is performed automatically after the wrapped read of data within the first memory area.

Abstract: Disclosed herein are system, method, and computer program product embodiments for accessing data of a memory. A method embodiment operates by receiving one or more requests for data stored across at least a first memory area and a second memory area of a memory. The method continues with performing, by at least one processor, a wrapped read of data within a first memory area of the memory. The method then performs, by the at least one processor, a continuous read of data within a second memory area of the memory, the second memory area being adjacent to the first memory area. The continuous read starts at a first boundary of the second memory area, and is performed automatically after the wrapped read of data within the first memory area.

Abstract: A method of outputting an input position of a touch panel is provided which can output an input position intended by an operator even if two or more different input positions are detected. When an input operation on a position different from a first input position is detected in a scan cycle after output of the first input position, the input position where the new input operation is detected is output as a second input position. Even if input operations on two or more different positions are simultaneously detected, only one input position is output.

Abstract: Systems and methods are provided to implement a memory device that includes a memory array having a plurality of sectors, a non-volatile memory that stores sector state information, and a memory controller that performs wear leveling according to the sector state information. The sector state information can specify respective states for respective sectors of the plurality of sectors of the memory array. The memory controller, based on the states of respective sectors, determines whether or not to swap contents of the sectors during wear leveling, thereby reducing write amplification effects.

Abstract: A method of outputting an input position of a touch panel is provided which can output an input position intended by an operator even if two or more different input positions are detected. When an input operation on a position different from a first input position is detected in a scan cycle after output of the first input position, the input position where the new input operation is detected is output as a second input position. Even if input operations on two or more different positions are simultaneously detected, only one input position is output.

Abstract: A data input terminal device is configured to be connected via a communication cable with a host computer from one of two connectors each associated with a distinct communications interface. The data terminal input device is configured to select the appropriate communications interface without additional intervention by a user. An interface selecting means selects the appropriate communications interface by detecting a connection state between the host computer and one of the two communication interfaces, and selecting the appropriate communications interface based on the detection result.

Abstract: A data input terminal device is configured to be connected via a communication cable with a host computer from one of two connectors each associated with a distinct communications interface. The data terminal input device is configured to select the appropriate communications interface without additional intervention by a user. An interface selecting means selects the appropriate communications interface by detecting a connection state between the host computer and one of the two communication interfaces, and selecting the appropriate communications interface based on the detection result.

Abstract: The present invention provides a pointing input device, which sequentially outputs pointing position data indicating a pointing input position and push detection data from a push by the same pen or finger used for a pointing input. The pointing input device includes a display panel for displaying any pointing input information and an optical touch panel. The optical touch panel detects the pointing input in an input operation area, through which a display area is visible, and outputs the pointing position data. Piezoelectric substrates are attached to a transparent protective plate protecting the top surface of the display panel. When an operator pushes the transparent protective plate disposed at the lower part of the optical touch panel while carrying out the pointing input, the piezoelectric substrates output electric signals by which the push is judged. Then, the push detection data is outputted with the pointing position data.