Abstract: A semiconductor device includes a transmitter, a termination resistance adjusting section, a transmitter control section and a control signal generating section. The transmitter has two output terminals and operates based on a control current. The termination resistance adjusting section is connected with the output terminals of the transmitter and applies a termination resistance adjusted in response to a control signal to each of the output terminals of the transmitter. The transmitter control section supplies the control current to the transmitter in response the control signal. The control signal generating section compares a first voltage corresponding to an external resistance and a second voltage corresponding to an internal resistance whose precision is lower than that of the external resistance, and outputs the control signal to the termination resistance adjusting section and the transmitter control section based on the comparing result.

Abstract: A signal detecting circuit includes first and second differential amplifiers and a differential exclusive-OR circuit. The first differential amplifier is configured to amplify a differential input signal and to output first positive and inversion phase output signals. The second differential amplifier is configured to amplify the differential input signal and to output second positive and inversion phase output signals. A common mode voltage of the second positive and inversion phase signals is shifted. The differential exclusive-OR circuit is configured to compare the first positive phase output signal and the second inversion phase output signal, and the second positive phase output signal and the first inversion phase output signal, and to output an exclusive logical summation of the comparing results as a positive phase exclusive-OR output signal.

Abstract: A semiconductor device includes a transmitter, a termination resistance adjusting section, a transmitter control section and a control signal generating section. The transmitter has two output terminals and operates based on a control current. The termination resistance adjusting section is connected with the output terminals of the transmitter and applies a termination resistance adjusted in response to a control signal to each of the output terminals of the transmitter. The transmitter control section supplies the control current to the transmitter in response the control signal. The control signal generating section compares a first voltage corresponding to an external resistance and a second voltage corresponding to an internal resistance whose precision is lower than that of the external resistance, and outputs the control signal to the termination resistance adjusting section and the transmitter control section based on the comparing result.

Abstract: A signal detecting circuit includes first and second differential amplifiers and a differential exclusive-OR circuit. The first differential amplifier is configured to amplify a differential input signal and to output first positive and inversion phase output signals. The second differential amplifier is configured to amplify the differential input signal and to output second positive and inversion phase output signals. A common mode voltage of the second positive and inversion phase signals is shifted. The differential exclusive-OR circuit is configured to compare the first positive phase output signal and the second inversion phase output signal, and the second positive phase output signal and the first inversion phase output signal, and to output an exclusive logical summation of the comparing results as a positive phase exclusive-OR output signal.

Abstract: A time card may have first and second card identifying sections disposed on opposite faces of the time card. The first card identifying section stores a most significant value of an identification of the time card, and the second card identifying section stores a least significant value of the card's identification. When combined to form a single value, the most and least significant values provide the time card identification. Also, a printing position indicator on the card identifies an initial printing position for the first and second card identifying sections to a time card recorder.

Abstract: An ID of the time card TK is divided to a plurality of ID marks in the form of at least two ID marks VN and VN′. Eeach of the divided IDs is provided to a front face T1 and a rear face T2. The divided ID marks VN and VN′ are read by mark sensors 12 and 13 of the time recorder TK. The read ID codes are combined as one ID code by reading of the sensors 12 and 13 and a working infomation such as attendace and leaving informations corresponding to the combined ID code is stored in a memory 21 and are printed to a predetermined printing column R of the time card TK. Accodingly,it is possible to provide a time card enabling to draw up a large numbers of ID codes and a time recorder system which makes the processing speed to fast and enables to fabricate a smoll sized time recorder, by constituting the time recorder enabling the reading of an ID and the printing of the ID during movement of the time card toward a inserting direction.