Patents by Inventor Yuichi Iwaya

Yuichi Iwaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240135005
    Abstract: This invention provides a method of managing secret information that ensures that key information in the discard phase can be invalidated and that the system cannot be started. In method of managing secret information in a semiconductor device, the semiconductor device has an OTP (One Time Programmable) module, a security module and a processor. The OTP module further has an OTP memory for storing a secret information and a lifecycle flag for defining an operation phase and a discard phase, a sequencer for reading information stored in the OTP memory and a register for storing the information read by the sequencer. The security module performs a process by the secret information. The processor requests the process to the security module when changing the operation phase to the discard phase and sends a request to the security module to invalidate the secret information.
    Type: Application
    Filed: August 14, 2023
    Publication date: April 25, 2024
    Inventors: Akira HAMAGUCHI, Yuichi IWAYA
  • Publication number: 20240089097
    Abstract: When the external storage itself is replaced by a legitimate old key by a malicious third party, the security IP cannot recognize that it is the old key and can be easily rolled back, that is, the old key is regarded as the legitimate key and operates. An OTP is provided in the SoC, and the version of the key ring is managed in one control table area. Specifically, predetermined information that is updated in synchronization with the key update is written in the management table area of the OTP, and an authentication value is calculated by associating the predetermined information with a key ring including the update key. The calculated authentication value is added and registered when registering the key ring.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Inventors: Takahiko SUGAHARA, Yuichi IWAYA, Akira HAMAGUCHI
  • Patent number: 10581682
    Abstract: It is possible to update firmware of domain masters during travelling. An in-vehicle communication system includes a plurality of domain masters, and a redundant domain master configured to be able to perform alternative operations of the plurality of domain masters. The domain masters transmits operation information to the redundant domain master prior to update of firmware. The redundant domain master executes the alternative operation of the domain master using the received operation information. The domain master receives, after the update of the firmware, operation information generated in the alternative operation from the redundant domain master and operates in the updated firmware.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 3, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki Ikeda, Yuichi Iwaya, Minoru Uemura, Tatsuya Ishikawa
  • Patent number: 10353451
    Abstract: In a system using a device not adapted to a single wire bus, a semiconductor device includes an external terminal to be coupled to a power source terminal of an external device, a port that supplies a power source voltage for the external device to the external terminal, a power manager that controls an output of the port, and a CPU that controls an operation of the power manager.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: July 16, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuya Ishikawa, Yoshiaki Daimon, Norihiko Ishizaki, Yuichi Iwaya
  • Publication number: 20180212822
    Abstract: It is possible to update firmware of domain masters during travelling. An in-vehicle communication system includes a plurality of domain masters, and a redundant domain master configured to be able to perform alternative operations of the plurality of domain masters. The domain masters transmits operation information to the redundant domain master prior to update of firmware. The redundant domain master executes the alternative operation of the domain master using the received operation information. The domain master receives, after the update of the firmware, operation information generated in the alternative operation from the redundant domain master and operates in the updated firmware.
    Type: Application
    Filed: December 18, 2017
    Publication date: July 26, 2018
    Inventors: Hiroyuki IKEDA, Yuichi IWAYA, Minoru UEMURA, Tatsuya ISHIKAWA
  • Publication number: 20170090540
    Abstract: In a system using a device not adapted to a single wire bus, a circuit such as a power source circuit for the device is needed. A semiconductor device includes an external terminal to be coupled to a power source terminal of an external device, a port that supplies a power source voltage for the external device to the external terminal, a power manager that controls an output of the port, and a CPU that controls an operation of the power manager.
    Type: Application
    Filed: August 11, 2016
    Publication date: March 30, 2017
    Inventors: Tatsuya ISHIKAWA, Yoshiaki DAIMON, Norihiko ISHIZAKI, Yuichi IWAYA
  • Patent number: 7652944
    Abstract: A semiconductor device is composed of a first circuit receiving a first power supply voltage; and a second circuit receiving a second power supply voltage. The second power supply voltage is higher than the first power supply voltage. Such device arrangement is effective for reducing the soft error rate, when the second circuit is more susceptive to a soft error than the first circuit, especially when the second circuit is a memory device.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: January 26, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yuichi Iwaya
  • Publication number: 20060279318
    Abstract: A semiconductor device is composed of a first circuit receiving a first power supply voltage; and a second circuit receiving a second power supply voltage. The second power supply voltage is higher than the first power supply voltage. Such device arrangement is effective for reducing the soft error rate, when the second circuit is more susceptive to a soft error than the first circuit, especially when the second circuit is a memory device.
    Type: Application
    Filed: June 12, 2006
    Publication date: December 14, 2006
    Inventor: Yuichi Iwaya