Patents by Inventor Yuichi Kawabata

Yuichi Kawabata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230061789
    Abstract: According to one embodiment, a search information processing device includes processing circuitry. The processing circuitry is configured to set disease information of a patient. The processing circuitry is configured to extract descriptions corresponding to the disease information from each of search results of a search site on the Internet. The processing circuitry is configured to append a reliability degree to each of the search results based on the extracted descriptions and evidence information for the disease information.
    Type: Application
    Filed: August 31, 2022
    Publication date: March 2, 2023
    Applicant: Canon Medical Systems Corporation
    Inventors: Katsuhiko FUJIMOTO, Yuichi KAWABATA
  • Publication number: 20220208387
    Abstract: A medical information processing apparatus comprises processing circuitry. The processing circuitry obtains from each of the patients entering a facility, identification information. The processing circuitry extracts when it is discovered that at least one of the patients has contracted a predetermined disease, an action taken in each of positions in the facility by a target patient who has contracted the disease, from action history information recording actions taken in the facility by each of the patients, on the basis of the identification information of the target patient. The processing circuitry calculates with respect to each of the positions in the facility, a first risk value of a risk imposed by the disease on a surrounding environment, on the basis of the actions of the target patient. The processing circuitry generates a risk map indicating the first risk values so as to be kept in association with the positions.
    Type: Application
    Filed: December 7, 2021
    Publication date: June 30, 2022
    Applicant: CANON MEDICAL SYSTEMS CORPORATION
    Inventors: Yuichi KAWABATA, Katsuhiko FUJIMOTO, Fuminori FUJITA, Michitaka SUGAWARA, Mariko SHIBATA
  • Publication number: 20220130556
    Abstract: A health management apparatus according to an embodiment is provided with processing circuitry. The processing circuitry is configured to acquire vital data and activity history information of a subject. The processing circuitry is configured to estimate a disease candidate of the subject based on the acquired vital data and the acquired activity history information. The processing circuitry is configured to cause a display, a speaker, or a terminal to output a notification regarding the estimated disease candidate or an interview item for determining a disease of the subject from the disease candidate. The activity history information includes at least information on a temperature of a space around the subject, information on a movement history of the subject, and a history of position information of the subject.
    Type: Application
    Filed: October 27, 2021
    Publication date: April 28, 2022
    Applicant: CANON MEDICAL SYSTEMS CORPORATION
    Inventors: Fuminori FUJITA, Yuichi KAWABATA, Kei MORI, Junko SHIBATA
  • Publication number: 20220084194
    Abstract: A computer program causes a computer to execute processing for acquiring examination point information regarding an examination point included in an examination target portion using an endoscope, acquiring an endoscopic image captured by the endoscope, determining whether the endoscope has reached the examination point on the basis of image analysis of the acquired endoscopic image, and outputting a notification in a case where the endoscope has reached the examination point.
    Type: Application
    Filed: August 2, 2019
    Publication date: March 17, 2022
    Applicant: HOYA CORPORATION
    Inventor: Yuichi KAWABATA
  • Patent number: 9122892
    Abstract: A protection device controlling an external device is provided having a mode detector, security data, a data detector, and a controller. The external device operates with operation modes that include a user mode that is used when the external device is operated by a user, and a manufacturer mode that is used when the external device is operated by someone other than the user. The mode detector detects an operation mode of the external device. The security data is input to the protection device. The data detector detects input of the security data. The controller restricts certain functions of the external device when the data detector does not detect input of the security data while the external device is in the manufacturer mode.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: September 1, 2015
    Assignee: HOYA CORPORATION
    Inventor: Yuichi Kawabata
  • Publication number: 20120311701
    Abstract: A protection device controlling an external device is provided having a mode detector, security data, a data detector, and a controller. The external device operates with operation modes that include a user mode that is used when the external device is operated by a user, and a manufacturer mode that is used when the external device is operated by someone other than the user. The mode detector detects an operation mode of the external device. The security data is input to the protection device. The data detector detects input of the security data. The controller restricts certain functions of the external device when the data detector does not detect input of the security data while the external device is in the manufacturer mode.
    Type: Application
    Filed: May 17, 2012
    Publication date: December 6, 2012
    Applicant: HOYA CORPORATION
    Inventor: Yuichi KAWABATA
  • Patent number: 4498022
    Abstract: An output buffer circuit capable of three-output states of high and low levels and a high impedance. The output buffer circuit includes a detector circuit for detecting that a power source voltage for the buffer circuit is particularly high and for turning the output of the buffer circuit to the high impedance state when the high voltage is detected.
    Type: Grant
    Filed: December 11, 1981
    Date of Patent: February 5, 1985
    Assignee: Fujitsu Limited
    Inventors: Kazumi Koyama, Toshitaka Fukushima, Yuichi Kawabata
  • Patent number: 4424582
    Abstract: A semiconductor memory device which writes information by rendering particular memory cells conductive or non-conductive, wherein, when a selected memory cell is to be read out, a power supply voltage is applied to the collector of a transistor which feeds a base current to a final stage transistor of a decoder circuit which is connected to word lines, and when information is to be written in, a voltage higher than the power supply voltage is applied to the same collector.
    Type: Grant
    Filed: April 21, 1980
    Date of Patent: January 3, 1984
    Assignee: Fujitsu Limited
    Inventors: Toshitaka Fukushima, Kazumi Koyama, Kouji Ueno, Tamio Miyamura, Yuichi Kawabata
  • Patent number: 4347584
    Abstract: A PROM device having the improved bit address decoders composed of a plurality of AND gates, each of the AND gates comprising PNP type transistors, to each base of which is applied an address signal from the bit address inverters. Each collector of these transistors is connected to ground, and each emitter is connected to the output terminal of the bit address decoder.
    Type: Grant
    Filed: April 21, 1980
    Date of Patent: August 31, 1982
    Assignee: Fujitsu Limited
    Inventors: Toshitaka Fukushima, Kazumi Koyama, Kouji Ueno, Yuichi Kawabata, Tamio Miyamura
  • Patent number: 4319341
    Abstract: A program circuit for permanently storing data into a programmable read only memory. A programming current (received from an external source) is connected to the selected bit line through a Darlington pair which is controlled by the bit decoding circuitry. Thus, the bit decoding circuitry is not required to pass the large programming current, and the programming current is not significantly shunted away from the selected bit line. To facilitate use of the Darlington configuration, a constant current source is provided for each bit line within a set of bit lines. The program circuit includes at least one switching means for connecting the program current to a selected bit line, a bit decoder connected to the control inputs of the switching means for selecting a bit line in response to the addressing signals input to the bit decoder and a control current supplying means for supplying a control current to the control inputs of the switching means.
    Type: Grant
    Filed: April 21, 1980
    Date of Patent: March 9, 1982
    Assignee: Fujitsu Limited
    Inventors: Toshitaka Fukushima, Kazumi Koyama, Kouji Ueno, Tamio Miyamura, Yuichi Kawabata
  • Patent number: 4319300
    Abstract: A screw-in station protector assembly includes a carrier housing containing a shorting cage which is biased by a compression to urge the cage and gas tube arrester assembly outwardly. The gas tube assembly contained within the cage includes a two electrode gas tube. The gas tube is within a jacket which forms a sealed external back-up air gap protector. The screw-in-assembly is particularly adapted for retro-fitting/replacement of carbon block arresters without modification.
    Type: Grant
    Filed: November 13, 1979
    Date of Patent: March 9, 1982
    Assignees: TII Industries, Inc., Fujitsu Limited
    Inventors: John Napiorkowski, Raymond D. Jones, Toshitaka Fukushima, Kazumi Koyama, Kouji Ueno, Tamio Miyamura, Yuichi Kawabata