Abstract: A flame detector in which an infrared ray sensor having a specific infrared ray sensitivity and a visible ray sensor having a specific visible ray sensitivity are provided and output signals from both sensors are amplified by amplifiers, which in turn provide output signals to a phase discriminator circuit, the output signal from the amplifier for the infrared sensor output being also fed to a rectifier circuit for rectifying only a predetermined level or higher portion of the amplified output; an output signal from the rectifier circuit is fed to an integrator circuit and also fed to another integrator circuit through a switch which is opened when the output level of the phase discriminator circuit is "H"; then output signals from the integrator circuits are compared by a comparator and at the same time the output signal from said another integrator circuit is compared with a preset value by a comparator; and output signals from both comparators are fed to a control circuit which issues an alarm when the out

Abstract: A double precision multiplyer for performing the multiplication of two double precision data using a 2's complement single precision multiplier. The 2n-1 bit double precision data is divided into one single precision data formed by taking the upper n bits of the double precision data and another single precision data formed by adding a "0" bit before the most significant bit of the remaining n-1 bits of the double precision data. Apparatus for performing the double precision multiplication thereby eliminates the necessity of discriminating the sign bit and enhances the speed of the double precision multiplication.

Abstract: A digital circuit for executing an arithmetic operation includes an overflow processing capability. The overflow processing is performed by a shifter to correct a decimal point. The shifter is used to shift a result of the arithmetic operation with an overflow and to shift a data to be operated by an arithmetic unit. The result and the data are applied to the shifter via a multiplexer, and either one of them is transferred to the shifter. The shifter is controlled such that the result of the arithmetic operation is shifted by one bit, while the data is shifted according to the number of overflows. As the result, the digital circuit can perform an arithmetic operation at a high speed by means of a simple hardware element.

Abstract: Overflow monitoring circuitry for an arithmetic unit offsets consecutive positive and negative overflows against one another to eliminate unnecessary overflow compensation during an arithmetic operation. In a first embodiment, an up/down counter is used to count positive overflows in one direction and negative overflows in another, with the value of the counter at the end of the arithmetic operation indicating the net overflow, if any has occurred, and the most significant bit of the counter representing the direction of any net overflow. In a second embodiment, logic circuitry offsets alternate positive and negative overflows against one another but will provide an overflow signal if either an odd number of overflows occurs or if two consecutive overflows in one direction occur during the arithmetic operation.

Abstract: An improved random access memory permits non-CPU involved, direct access for data read out to a portion of memory - as for information display purposes. The composite memory (and thereby also apparatus employing such a memory) may thus be more readily and inexpensively fabricated, not requiring either a dedicated, separate display register or stored instructions for memory-to-display register information transfer. The memory includes first and second portions each capable of central process or access, the second memory segment being subject to direct, non-CPU aided addressing when not engaged by the CPU.