Patents by Inventor Yuichi Kishida

Yuichi Kishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6170039
    Abstract: In a memory system having a plurality of banks which forms interleave groups for independently forming an interleave, when a memory error is detected in an operating system resident space, the group having the error is interchanged with another group that has not had any error yet. After a group interchange, a page having the error is also deallocated. When a determination is made that the group interchange causes deterioration of performance, a bank deallocation can be also executed. As this criterion for determination, it is possible to employ a policy that a bank is deallocated when a capacity of a bank including an erroneous sub-bank is equal to or less than a predetermined rate of all the memory capacity and an interleaving factor is less than the interleaving factor of an interchange partner after the bank deallocation.
    Type: Grant
    Filed: May 18, 1998
    Date of Patent: January 2, 2001
    Assignee: NEC Corporation
    Inventor: Yuichi Kishida