Patents by Inventor Yuichi Kitamura

Yuichi Kitamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9715522
    Abstract: A storage unit stores update data corresponding to transactions being executed and indicating updating processes yet to be reflected in a database. A control unit generates a list indicating transactions. When apparatuses executing transactions are switched from an information processing apparatus to another information processing apparatus, the control unit transmits the list to the other information processing apparatus, and migrates the update data to the other information processing apparatus based on the list.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: July 25, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Atsuhito Hirose, Toshihiro Kawakami, Akihiro Yamamoto, Tamaki Tanaka, Toshiaki Yamada, Yuichi Kitamura
  • Publication number: 20150278333
    Abstract: A storage unit stores update data corresponding to transactions being executed and indicating updating processes yet to be reflected in a database. A control unit generates a list indicating transactions. When apparatuses executing transactions are switched from an information processing apparatus to another information processing apparatus, the control unit transmits the list to the other information processing apparatus, and migrates the update data to the other information processing apparatus based on the list.
    Type: Application
    Filed: March 16, 2015
    Publication date: October 1, 2015
    Inventors: Atsuhito HIROSE, Toshihiro KAWAKAMI, Akihiro YAMAMOTO, Tamaki TANAKA, Toshiaki YAMADA, Yuichi KITAMURA
  • Patent number: 7391039
    Abstract: A secondary electron image generated by an electron beam is detected by a secondary electron/secondary ion detector while a silicon substrate is etched by a focused ion beam from a back surface of a semiconductor chip. A time point where the electron beam transmits through the silicon substrate, a contrast of a secondary electron image of a separation layer, a polysilicon layer and the like is detected by a picture image processing system is assumed to be a processing end point. At this time, by changing a setting for an acceleration voltage of the electron beam, an arbitrary remaining silicon thickness can be obtained.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: June 24, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yuichi Kitamura, Naoto Sugiura
  • Publication number: 20060255270
    Abstract: A secondary electron image generated by an electron beam is detected by a secondary electron/secondary ion detector while a silicon substrate is etched by a focused ion beam from a back surface of a semiconductor chip. A time point where the electron beam transmits through the silicon substrate, a contrast of a secondary electron image of a separation layer, a polysilicon layer and the like is detected by a picture image processing system is assumed to be a processing end point. At this time, by changing a setting for an acceleration voltage of the electron beam, an arbitrary remaining silicon thickness can be obtained.
    Type: Application
    Filed: March 10, 2006
    Publication date: November 16, 2006
    Inventors: Yuichi Kitamura, Naoto Sugiura
  • Publication number: 20060071182
    Abstract: The present invention relates to a method (apparatus) of processing a semiconductor apparatus, wherein a processing beam is irradiated on a semiconductor apparatus comprising an insulation film and a conductor embedded in the insulation film while the insulation film is scanned from a surface side thereof so that the insulation film and the conductor are burned and cut. The processing method (apparatus) comprises a scanning region setting step for setting a scanning region of the processing beam to a region where a scanning column direction thereof traverses a cut section of the conductor and a beam scanning step for irradiating the processing beam for scanning along the set scanning region, wherein the processing beam used for scanning a final scanning column is supplied with a dosage capable of eliminating a conductive residue generated by the irradiation of the processing beam on the conductor and attached to a cut end surface facing the final scanning column in the beam scanning step.
    Type: Application
    Filed: October 4, 2005
    Publication date: April 6, 2006
    Inventors: Naoto Sugiura, Yuichi Kitamura
  • Patent number: 6784490
    Abstract: A high-voltage MOS transistor wherein a dopant concentration of a source offset region is set lower than a dopant concentration of a drain offset region whereby a resistance value of the resource region is set independently of a resistance value of the drain region in such a manner as to maintain a high sustaining breakdown voltage of the high-voltage MOS transistor, which is based on a voltage of the source offset region and a voltage of a substrate region directly under a gate insulating film during operation of the high-voltage MOS transistor.
    Type: Grant
    Filed: September 19, 2000
    Date of Patent: August 31, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Haruko Inoue, Yuichi Kitamura