Patents by Inventor Yuichi Mabuchi
Yuichi Mabuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10014793Abstract: An imbalance of control signals between two power semiconductor elements is reduced. A first power semiconductor module and a second power semiconductor module are arranged in a predetermined direction along a surface of a control signal wiring circuit board, each of longitudinal directions of the first power semiconductor module and the second power semiconductor module along the surface of the control signal wiring circuit board is a predetermined direction, and, in a first control signal wiring, a distance between an external control signal terminal and a second control signal terminal is equal to a distance between the external control signal terminal and a first control signal terminal.Type: GrantFiled: March 10, 2014Date of Patent: July 3, 2018Assignee: Hitachi, Ltd.Inventors: Akira Mima, Yukio Hattori, Tetsuya Kawashima, Yuichi Mabuchi, Daisuke Matsumoto, Hiroshi Kamiduma
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Publication number: 20170093299Abstract: In order to reduce the size of an isolation transformer, the present invention provides a power conversion device including: a first inverter unit for obtaining a DC input and giving a high frequency output; an LLC transformer for converting the voltage of the high frequency output of the first inverter unit; a rectifier unit for DC-converting the voltage of the output of the LLC transformer; a second inverter unit for converting the DC output of the rectifier unit into AC; and a control circuit for obtaining the gate power of a semiconductor device configuring the second inverter unit through a power supply transformer for the control circuit that is connected in parallel to the secondary circuit of the LLC transformer.Type: ApplicationFiled: August 24, 2016Publication date: March 30, 2017Inventors: Yasuaki NORIMATSU, Akihiko KANODA, Yuichi MABUCHI, Takae SHIMADA, Mitsuhiro KADOTA, Yuki KAWAGUCHI, Akira YONEKAWA
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Publication number: 20160373017Abstract: An imbalance of control signals between two power semiconductor elements is reduced. A first power semiconductor module and a second power semiconductor module are arranged in a predetermined direction along a surface of a control signal wiring circuit board, each of longitudinal directions of the first power semiconductor module and the second power semiconductor module along the surface of the control signal wiring circuit board is a predetermined direction, and, in a first control signal wiring, a distance between an external control signal terminal and a second control signal terminal is equal to a distance between the external control signal terminal and a first control signal terminal.Type: ApplicationFiled: March 10, 2014Publication date: December 22, 2016Inventors: Akira MIMA, Yukio HATTORI, Tetsuya KAWASHIMA, Yuichi MABUCHI, Daisuke MATSUMOTO, Hiroshi KAMIDUMA
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Patent number: 8205105Abstract: An electronic device comprising: a wiring substrate having a first power-supply wiring to which a first power-supply potential is applied and a second power-supply wiring to which a second power-supply potential lower than the first power-supply potential is applied; a microcomputer having first and second power-supply terminals in which the first power-supply terminal is connected to the first power-supply wiring and the second power-supply terminal is connected to the second power-supply wiring; and a connector connected to the first and second power-supply wirings, wherein an inductor element for correcting an impedance error of the first and second wirings is connected in series to either one of the first and second power-supply wirings. According to such configuration, unnecessary electromagnetic radiation posed by a common current can be suppressed.Type: GrantFiled: February 8, 2011Date of Patent: June 19, 2012Assignee: Renesas Electronics CorporationInventors: Atsushi Nakamura, Toru Hayashi, Yuichi Mabuchi
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Publication number: 20110126030Abstract: An electronic device comprising: a wiring substrate having a first power-supply wiring to which a first power-supply potential is applied and a second power-supply wiring to which a second power-supply potential lower than the first power-supply potential is applied; a microcomputer having first and second power-supply terminals in which the first power-supply terminal is connected to the first power-supply wiring and the second power-supply terminal is connected to the second power-supply wiring; and a connector connected to the first and second power-supply wirings, wherein an inductor element for correcting an impedance error of the first and second wirings is connected in series to either one of the first and second power-supply wirings. According to such configuration, unnecessary electromagnetic radiation posed by a common current can be suppressed.Type: ApplicationFiled: February 8, 2011Publication date: May 26, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Atsushi Nakamura, Toru Hayashi, Yuichi Mabuchi
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Patent number: 7900066Abstract: An electronic device comprising: a wiring substrate having a first power-supply wiring to which a first power-supply potential is applied and a second power-supply wiring to which a second power-supply potential lower than the first power-supply potential is applied; a microcomputer having first and second power-supply terminals in which the first power-supply terminal is connected to the first power-supply wiring and the second power-supply terminal is connected to the second power-supply wiring; and a connector connected to the first and second power-supply wirings, wherein an inductor element for correcting an impedance error of the first and second wirings is connected in series to either one of the first and second power-supply wirings. According to such configuration, unnecessary electromagnetic radiation posed by a common current can be suppressed.Type: GrantFiled: April 13, 2005Date of Patent: March 1, 2011Assignee: Renesas Electronics CorporationInventors: Atsushi Nakamura, Toru Hayashi, Yuichi Mabuchi
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Publication number: 20100283124Abstract: Provided is a semiconductor device in which impedances of power-supply wiring/GND wiring are matched with each other inside the semiconductor device to reduce a noise current without depending on a mounting layout of a circuit board. In a semiconductor device according to a typical embodiment of the present invention including: a package board; a semiconductor chip; a power-supply wiring; and a GND wiring, the semiconductor device includes a conductive plate, and further includes a first impedance adjusting element and a second impedance adjusting element. Parasitic capacitances of the power-supply wiring and the GND wiring are determined by the conductive plate, and the impedances of the power-supply wiring and the GND wiring are adjusted by the first impedance adjusting element and the second impedance adjusting element.Type: ApplicationFiled: January 7, 2009Publication date: November 11, 2010Applicant: Renesas Electronics CorporationInventors: Aya Ohmae, Yuichi Mabuchi, Atsushi Nakamura
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Publication number: 20090206951Abstract: An electronic device comprising: a wiring substrate having a first power-supply wiring to which a first power-supply potential is applied and a second power-supply wiring to which a second power-supply potential lower than the first power-supply potential is applied; a microcomputer having first and second power-supply terminals in which the first power-supply terminal is connected to the first power-supply wiring and the second power-supply terminal is connected to the second power-supply wiring; and a connector connected to the first and second power-supply wirings, wherein an inductor element for correcting an impedance error of the first and second wirings is connected in series to either one of the first and second power-supply wirings. According to such configuration, unnecessary electromagnetic radiation posed by a common current can be suppressed.Type: ApplicationFiled: April 13, 2005Publication date: August 20, 2009Inventors: Atsushi Nakamura, Toru Hayashi, Yuichi Mabuchi
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Patent number: 7516823Abstract: An electric braking apparatus including a motor for pressing brake pads on disks, a metal housing for housing the motor, a positive-polarity power line for transmitting power from a battery to the electric motor, a negative-polarity ground line for connecting the electric motor to the ground of a vehicle, and a conductor for electrically connecting the metal housing to the negative polarity of battery or the negative-polarity of an inverter.Type: GrantFiled: January 22, 2008Date of Patent: April 14, 2009Assignee: Hitachi, Ltd.Inventors: Kenji Kikuchi, Yuichi Kuramochi, Yuichi Mabuchi
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Publication number: 20080236964Abstract: An electric braking apparatus including a motor for pressing brake pads on disks, a metal housing for housing the motor, a positive-polarity power line for transmitting power from a battery to the electric motor, a negative-polarity ground line for connecting the electric motor to the ground of a vehicle, and a conductor for electrically connecting the metal housing to the negative polarity of battery or the negative-polarity of an inverter.Type: ApplicationFiled: January 22, 2008Publication date: October 2, 2008Applicant: Hitachi, Ltd.Inventors: Kenji Kikuchi, Yuichi Kuramochi, Yuichi Mabuchi
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Patent number: 7095117Abstract: A semiconductor device has a reduced number of external power terminals and is scaled down while suppressing power noise, and an electronic device is efficiently equipped with a bypass condenser. A package substrate has, on its surface, a semiconductor chip having a plurality of output circuits and at least one electrode for supplying a voltage to each of the output circuits, and is provided with external terminals on its back surface and has a plurality of wiring layers.Type: GrantFiled: September 14, 2004Date of Patent: August 22, 2006Inventors: Motoo Suwa, Yuichi Mabuchi, Atsushi Nakamura, Hideshi Fukumoto
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Patent number: 6871334Abstract: The invention provides a method of calculating an equivalent circuit, which reduces the number of elements constituting a network to a large extent with a target accuracy secured. The method of the invention calculates an equivalent circuit by a computer, with regard to an object that has a conductor, a dielectric to support the conductor, and plural input/output terminals to the outside.Type: GrantFiled: October 16, 2002Date of Patent: March 22, 2005Assignee: Hitachi, Ltd.Inventors: Yuichi Mabuchi, Hideshi Fukumoto
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Publication number: 20050029648Abstract: A semiconductor device has a reduced number of external power terminals and is scaled down while suppressing power noise, and an electronic device is efficiently equipped with a bypass condenser. A package substrate has, on its surface, a semiconductor chip having a plurality of output circuits and at least one electrode for supplying a voltage to each of the output circuits, and is provided with external terminals on its back surface and has a plurality of wiring layers.Type: ApplicationFiled: September 14, 2004Publication date: February 10, 2005Applicant: Renesas Technology Corp.Inventors: Motoo Suwa, Yuichi Mabuchi, Atsushi Nakamura, Hideshi Fukumoto
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Patent number: 6803659Abstract: A semiconductor device is provided that reduces the number of external power terminals. The device is intended for a flip-chip type BGA (ball grid array) package. On the surface of the packet substrate are a plurality of output circuits each outputting a signal formed by an internal circuit, a first voltage supply electrode which supplies an operating voltage to the internal circuit and a plurality of second voltage supply electrodes which supply operating voltages to the output circuits. On the back surface of the package substrate are external terminals and a plurality of wiring layers.Type: GrantFiled: October 11, 2002Date of Patent: October 12, 2004Assignee: Renesas Technology Corp.Inventors: Motoo Suwa, Yuichi Mabuchi, Atsushi Nakamura, Hideshi Fukumoto
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Publication number: 20030109995Abstract: The invention provides a method of calculating an equivalent circuit, which reduces the number of elements constituting a network to a large extent with a target accuracy secured. The method of the invention calculates an equivalent circuit by a computer, with regard to an object that has a conductor, a dielectric to support the conductor, and plural input/output terminals to the outside.Type: ApplicationFiled: October 16, 2002Publication date: June 12, 2003Inventors: Yuichi Mabuchi, Hideshi Fukumoto
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Publication number: 20030080353Abstract: The present invention provides a semiconductor device which reduces the number of external power terminals and realizes its scale down while suppressing power noise, and an electronic device efficiently equipped with a bypass condenser.Type: ApplicationFiled: October 11, 2002Publication date: May 1, 2003Inventors: Motoo Suwa, Yuichi Mabuchi, Atsushi Nakamura, Hideshi Fukumoto