Patents by Inventor Yuichi Miyagawa
Yuichi Miyagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12002141Abstract: There is provided an image display apparatus that makes it possible to automatically orient a front face of a three-dimensional object represented by a three-dimensional image to a user. There are provided: a display unit that displays the three-dimensional image, by which the three-dimensional object appears to exist in a space partitioned by members configuring an outer surface, to be visually recognizable from a plurality of circumferential directions; a direction estimation section that estimates a direction in which a user exists as seen from the display unit; and a display control section that orients a front face of the three-dimensional object displayed by the display unit in the direction in which the user exists estimated by the direction estimation section.Type: GrantFiled: July 21, 2020Date of Patent: June 4, 2024Assignee: Sony Group CorporationInventors: Takanobu Omata, Kaoru Koike, Yuichi Miyagawa, Hisataka Izawa, Itaru Shimizu
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Publication number: 20240087205Abstract: There is provided an image display apparatus that makes it possible to automatically orient a front face of a three-dimensional object represented by a three-dimensional image to a user. There are provided: a display unit that displays the three-dimensional image, by which the three-dimensional object appears to exist in a space partitioned by members configuring an outer surface, to be visually recognizable from a plurality of circumferential directions; a direction estimation section that estimates a direction in which a user exists as seen from the display unit; and a display control section that orients a front face of the three-dimensional object displayed by the display unit in the direction in which the user exists estimated by the direction estimation section.Type: ApplicationFiled: July 21, 2020Publication date: March 14, 2024Applicant: SONY GROUP CORPORATIONInventors: Takanobu OMATA, Kaoru KOIKE, Yuichi MIYAGAWA, Hisataka IZAWA, Itaru SHIMIZU
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Patent number: 11914797Abstract: Provided is an image display apparatus that includes a display displaying a three-dimensional image such that a three-dimensional object looks as if in a space defined by a member constituting an external surface and that the three-dimensional object is visible from multiple directions around the display, a motion detector detecting a motion of the display caused by an external force, a motion calculation unit calculating a motion of the three-dimensional object caused by the motion of the display based on the motion detected by the motion detector, a display control unit changing the three-dimensional image displayed on the display based on the calculation by the motion calculation unit, and a force sense control unit causing a force sense presentation unit to present a sense of force based on the calculation by the motion calculation unit.Type: GrantFiled: July 21, 2020Date of Patent: February 27, 2024Assignee: SONY GROUP CORPORATIONInventors: Takanobu Omata, Kaoru Koike, Yuichi Miyagawa, Hisataka Izawa, Itaru Shimizu
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Patent number: 11829572Abstract: There is provided an image display apparatus that enables an intuitive operation even when a detection target is not able to be inserted into a first space in which a three-dimensional object is visually recognized. A position of a detection target is detected, and a display position of a pointer displayed by a display unit is moved on a basis of a position of the detection target that exists within a second space not overlapping the first space which is a space in which the three-dimensional object is displayed among the position of the detected detection target.Type: GrantFiled: October 1, 2020Date of Patent: November 28, 2023Assignee: SONY GROUP CORPORATIONInventors: Kaoru Koike, Itaru Shimizu, Takanobu Omata, Yuichi Miyagawa, Hisataka Izawa
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Publication number: 20220365658Abstract: There is provided an image display apparatus that enables an intuitive operation even when a detection target is not able to be inserted into a first space in which a three-dimensional object is visually recognized. A position of a detection target is detected, and a display position of a pointer displayed by a display unit is moved on a basis of a position of the detection target that exists within a second space not overlapping the first space which is a space in which the three-dimensional object is displayed among the position of the detected detection target.Type: ApplicationFiled: October 1, 2020Publication date: November 17, 2022Inventors: KAORU KOIKE, ITARU SHIMIZU, TAKANOBU OMATA, YUICHI MIYAGAWA, HISATAKA IZAWA
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Publication number: 20220365607Abstract: Provided is an image display apparatus that makes it possible to provide appropriate interaction with a user.Type: ApplicationFiled: July 21, 2020Publication date: November 17, 2022Inventors: TAKANOBU OMATA, KAORU KOIKE, YUICHI MIYAGAWA, HISATAKA IZAWA, ITARU SHIMIZU
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Patent number: 11481025Abstract: There is provided a display control apparatus including a control section configured to control an operation on an object in a position corresponding to an operating position recognized on the basis of a relation between multiple operating lines each displayed corresponding to an indicator body. The apparatus allows the object to be operated with as little motion as possible.Type: GrantFiled: November 19, 2019Date of Patent: October 25, 2022Assignee: SONY GROUP CORPORATIONInventors: Itaru Shimizu, Yuichi Miyagawa, Takanobu Omata, Kaoru Koike, Hisataka Izawa
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Publication number: 20220011853Abstract: There is provided a display control apparatus including a control section configured to control an operation on an object in a position corresponding to an operating position recognized on the basis of a relation between multiple operating lines each displayed corresponding to an indicator body. The apparatus allows the object to be operated with as little motion as possible.Type: ApplicationFiled: November 19, 2019Publication date: January 13, 2022Inventors: ITARU SHIMIZU, YUICHI MIYAGAWA, TAKANOBU OMATA, KAORU KOIKE, HISATAKA IZAWA
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Patent number: 10249565Abstract: A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.Type: GrantFiled: August 25, 2016Date of Patent: April 2, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuichi Miyagawa, Hideki Fujii, Kenji Furuya
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Publication number: 20160365316Abstract: A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.Type: ApplicationFiled: August 25, 2016Publication date: December 15, 2016Inventors: Yuichi MIYAGAWA, Hideki FUJII, Kenji FURUYA
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Patent number: 9461103Abstract: A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.Type: GrantFiled: August 13, 2014Date of Patent: October 4, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuichi Miyagawa, Hideki Fujii, Kenji Furuya
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Publication number: 20140346636Abstract: A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.Type: ApplicationFiled: August 13, 2014Publication date: November 27, 2014Inventors: Yuichi MIYAGAWA, Hideki FUJII, Kenji FURUYA
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Patent number: 8823134Abstract: A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.Type: GrantFiled: August 2, 2011Date of Patent: September 2, 2014Assignee: Renesas Electronics CorporationInventors: Yuichi Miyagawa, Hideki Fujii, Kenji Furuya
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Patent number: 8174102Abstract: A semiconductor device including: a substrate formed with a concave portion at one surface thereof; and a first semiconductor chip provided in the concave portion of the substrate and is adhered to the substrate by an underfill in the concave portion, wherein the concave portion includes a chip arrangement region in which the first semiconductor chip is arranged, and an adjustment region which protrudes from at least a portion of the periphery of the chip arrangement region when seen in a plan view at a height of at least a portion of a region where the first semiconductor chip is placed in a stacked direction of the substrate, and has different shapes from the chip arrangement region is provided.Type: GrantFiled: November 10, 2009Date of Patent: May 8, 2012Assignee: Renesas Electronics CorporationInventor: Yuichi Miyagawa
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Publication number: 20120032298Abstract: A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.Type: ApplicationFiled: August 2, 2011Publication date: February 9, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yuichi MIYAGAWA, Hideki FUJII, Kenji FURUYA
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Patent number: 7986035Abstract: A multilayer wiring substrate included in the semiconductor package includes: a first insulating layer and a second insulating layer, in which wiring layers are respectively provided on the upper and the lower surfaces; and; a core layer provided between the first insulating layer and the second insulating layer. The first insulating layer and the second insulating layer are constituted by different materials from each other.Type: GrantFiled: March 18, 2009Date of Patent: July 26, 2011Assignee: Renesas Electronics CorporationInventor: Yuichi Miyagawa
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Patent number: 7906854Abstract: A semiconductor device includes a semiconductor chip, a supporting body that is disposed below the semiconductor chip and supports the semiconductor chip, a spacer that is fixed onto the first semiconductor chip, and a substrate that is located below the first semiconductor chip and electrically connected to the semiconductor chip with a wire. At least a part of the peripheral portion of the semiconductor chip is an overhang portion that projects more laterally than the peripheral portion of the supporting body. A covering portion that covers a part of the upper surface of the overhang portion is formed in the spacer. The wire is connected to a region in the upper surface of the overhang portion, the region being lateral to the outermost periphery of the covering portion of the spacer and not being covered with the covering portion of the spacer.Type: GrantFiled: October 14, 2008Date of Patent: March 15, 2011Assignee: Renesas Electronics CorporationInventor: Yuichi Miyagawa
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Publication number: 20110049701Abstract: The semiconductor device includes a substrate; a semiconductor chip mounted over the substrate; resin encapsulating the semiconductor chip; and a heat dissipation material that is arranged over the semiconductor chip and in contact with the resin, wherein the resin includes a first resin region made of a first resin composition, a second resin region made of a second resin composition, and a mixed layer that is formed between the first and second resin regions and obtained by mixing the first resin composition and the second resin composition.Type: ApplicationFiled: September 1, 2010Publication date: March 3, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Yuichi MIYAGAWA
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Patent number: 7888809Abstract: A semiconductor device including a substrate, a semiconductor chip mounted on the substrate, and an encapsulation resin encapsulating the semiconductor chip, wherein the encapsulation resin contains a first resin region composed of a first resin composition, a second resin region composed of a second resin composition, and a mixed layer formed between the first resin region and the second resin region so as to have the first resin composition and the second resin composition mixed therein is provided.Type: GrantFiled: October 22, 2009Date of Patent: February 15, 2011Assignee: Renesas Electronics CorporationInventors: Yuichi Miyagawa, Takamitsu Noda, Hiroyasu Miyamoto, Jun Tsukano
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Publication number: 20100258955Abstract: The semiconductor device includes a substrate over one surface of which an electroless plating electrode film is formed; a semiconductor chip mounted over the one surface of the substrate; and a bonding wire which connects the semiconductor chip and one surface of the electroless plating electrode film, a recessed depth which is a difference between a lowermost height of a bonding portion of the one surface of the electroless plating electrode film to the bonding wire, and an uppermost height of the one surface other than the bonding portion being equal to or less than 1.5 ?m.Type: ApplicationFiled: April 9, 2010Publication date: October 14, 2010Applicant: NEC ELECTRONICS CORPORATIONInventors: YUICHI MIYAGAWA, HIDEYUKI HORII, KENTA OGAWA