Patents by Inventor Yuichi Miyahara
Yuichi Miyahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11949833Abstract: An object of one embodiment of the present invention is to accurately derive an inclination of a line image sensor. One embodiment of the present invention is an image reading apparatus including: a line image sensor in which reading elements for reading an image are arrayed in a predetermined direction; a first derivation unit configured to, based on read data acquired by reading a chart on which a plurality of dot patterns is printed with the line image sensor, derive coordinates of each of the plurality of dot patterns; a second derivation unit configured to derive an inclination angle of the line image sensor based on the coordinates derived by the first derivation unit; and a first calculation unit configured to calculate a first correction value for correcting the inclination of the line image sensor based on the inclination angle derived by the second derivation unit.Type: GrantFiled: October 13, 2021Date of Patent: April 2, 2024Assignee: Canon Kabushiki KaishaInventors: Yuki Kamio, Katsutoshi Miyahara, Yuichi Sato, Takahiro Ode
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Publication number: 20240079492Abstract: A semiconductor device includes a second deep layer between a first deep layer and first current distribution layer and a base region in an active region and in a part of an inactive region adjacent to the active region. The second deep layer has a second stripe portion including lines connecting to the base region and the first deep layer. The semiconductor device further includes a second current distribution layer between the first current distribution layer and the base region and arranged between the lines of the second stripe portion. The first deep layer has a first stripe portion including a plurality of lines, and each line has an end portion connecting to a frame-shaped portion and an inner portion on an inner side of the end portion. The width of the end portion is equal to or greater than the inner portion.Type: ApplicationFiled: November 10, 2023Publication date: March 7, 2024Inventors: Atsuya AKIBA, Yuichi TAKEUCHI, Kazuki ARAKAWA, Yusuke HAYAMA, Yasushi URAKAMI, Shinichiro MIYAHARA, Tomoo MORINO
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Patent number: 10992311Abstract: Provided is a delta-sigma AD converter including a delta-sigma modulating section that outputs a digital signal obtained by performing delta-sigma modulation with an oversampling ratio on an input analog signal; a digital filtering section that filters the digital signal with the oversampling ratio; a control terminal into which an external control signal is input; an output control section that performs control to output an output signal based on the filtered digital signal, according to the external control signal; and a setting section that sets the oversampling ratio based on interval information of the external control signal.Type: GrantFiled: July 9, 2020Date of Patent: April 27, 2021Assignee: Asahi Kasei Microdevices CorporationInventor: Yuichi Miyahara
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Publication number: 20200343906Abstract: Provided is a delta-sigma AD converter including a delta-sigma modulating section that outputs a digital signal obtained by performing delta-sigma modulation with an oversampling ratio on an input analog signal; a digital filtering section that filters the digital signal with the oversampling ratio; a control terminal into which an external control signal is input; an output control section that performs control to output an output signal based on the filtered digital signal, according to the external control signal; and a setting section that sets the oversampling ratio based on interval information of the external control signal.Type: ApplicationFiled: July 9, 2020Publication date: October 29, 2020Inventor: Yuichi MIYAHARA
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Patent number: 10720939Abstract: Provided is a delta-sigma AD converter including a delta-sigma modulating section that outputs a digital signal obtained by performing delta-sigma modulation with an oversampling ratio on an input analog signal; a digital filtering section that filters the digital signal with the oversampling ratio; a control terminal into which an external control signal is input; an output control section that performs control to output an output signal based on the filtered digital signal, according to the external control signal; and a setting section that sets the oversampling ratio based on interval information of the external control signal.Type: GrantFiled: June 12, 2019Date of Patent: July 21, 2020Assignee: Asahi Kasei Microdevices CorporationInventor: Yuichi Miyahara
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Publication number: 20190379392Abstract: Provided is a delta-sigma AD converter including a delta-sigma modulating section that outputs a digital signal obtained by performing delta-sigma modulation with an oversampling ratio on an input analog signal; a digital filtering section that filters the digital signal with the oversampling ratio; a control terminal into which an external control signal is input; an output control section that performs control to output an output signal based on the filtered digital signal, according to the external control signal; and a setting section that sets the oversampling ratio based on interval information of the external control signal.Type: ApplicationFiled: June 12, 2019Publication date: December 12, 2019Inventor: Yuichi MIYAHARA
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Patent number: 9432049Abstract: An A/D converter includes an incremental delta-sigma A/D modulator and a digital operation unit to which a signal from the A/D modulator is input. The A/D modulator includes an analog integrator configured to integrate input signals, a quantizer configured to quantize output signals of the analog integrator, a D/A converter configured to D/A convert an output of the quantizer, and a reset signal output device configured to reset the analog integrator and the digital operation unit. The analog integrator includes plural switched capacitors and a first analog integrator connected to the switched capacitors. The first analog integrator includes an operational amplifier connected to the switched capacitors and a feedback capacitor each connecting an input and an output of the operational amplifier.Type: GrantFiled: December 29, 2015Date of Patent: August 30, 2016Assignee: Asahi Kasei Microdevices CorporationInventors: Takato Katayama, Yuichi Miyahara, Kanya Sasaki
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Publication number: 20160197619Abstract: An A/D converter includes an incremental delta-sigma A/D modulator and a digital operation unit to which a signal from the A/D modulator is input. The A/D modulator includes an analog integrator configured to integrate input signals, a quantizer configured to quantize output signals of the analog integrator, a D/A converter configured to D/A convert an output of the quantizer, and a reset signal output device configured to reset the analog integrator and the digital operation unit. The analog integrator includes plural switched capacitors and a first analog integrator connected to the switched capacitors. The first analog integrator includes an operational amplifier connected to the switched capacitors and a feedback capacitor each connecting an input and an output of the operational amplifier.Type: ApplicationFiled: December 29, 2015Publication date: July 7, 2016Applicant: ASAHI KASEI MICRODEVICES CORPORATIONInventors: Takato KATAYAMA, Yuichi MIYAHARA, Kanya SASAKI
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Patent number: 9374104Abstract: There is provided a pipelined A/D converter in which plural stages Stage 1 to Stage N each including an MDAC (i.e., Multiplying DA Converter) are connected. The pipelined A/D converter is configured with a Gain-AMP (12) included in the MDAC for the SPM, MOS transistors (Mx1) and (Mx2) as a differential pair having output ends connected to a sampling capacitor CsI on a subsequent stage, MOS transistors (My1) and (My2) as a load unit connected to the differential pair, a current source (I3) configured to supply a current to the MOS transistors (Mx1) and (Mx2) as the differential pair, and current sources (I1) and (I2) configured to adjust the current flown across the MOS transistors (My1) and (My2) as the load unit.Type: GrantFiled: August 12, 2013Date of Patent: June 21, 2016Assignee: Asahi Kasei Microdevices CorporationInventor: Yuichi Miyahara
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Publication number: 20150229320Abstract: There is provided a pipelined A/D converter in which plural stages Stage 1 to Stage N each including an MDAC (i.e., Multiplying DA Converter) are connected. The pipelined A/D converter is configured with a Gain-AMP (12) included in the MDAC for the SPM, MOS transistors (Mx1) and (Mx2) as a differential pair having output ends connected to a sampling capacitor CsI on a subsequent stage, MOS transistors (My1) and (My2) as a load unit connected to the differential pair, a current source (I3) configured to supply a current to the MOS transistors (Mx1) and (Mx2) as the differential pair, and current sources (I1) and (I2) configured to adjust the current flown across the MOS transistors (My1) and (My2) as the load unit.Type: ApplicationFiled: August 12, 2013Publication date: August 13, 2015Applicant: ASAHI KASEI MICRODEVICES CORPORATIONInventor: Yuichi Miyahara
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Patent number: 6071337Abstract: A method and apparatus for producing crystals by the Czochralski method whereby the thermal history during crystal growth according to the CZ method can be controlled with ease and accuracy. The apparatus comprises a crucible for receiving a raw material, a heater for heating and melting the raw material, and a heat insulating cylinder disposed so as to surround the crucible and the heater, wherein a portion of the heat insulating cylinder that is located above an upper end of the heater is so configured that its inner diameter is larger than the outer diameter of the heater at its lower end, and that its inner diameter at its upper end is equal to or less than the inner diameter of the heater while its outer diameter is equal to or greater than the outer diameter of the heater. This apparatus is used to produce crystals and to control the temperature distribution inside the crystal producing apparatus or the thermal history of crystals.Type: GrantFiled: August 14, 1998Date of Patent: June 6, 2000Assignee: Shin-Etsu Handotai Co., LtdInventors: Masahiro Sakurada, Yuichi Miyahara, Tomohiko Ohta
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Patent number: 5745594Abstract: An imaging device for imaging an object is situated above the object. A downward-illumination device for emitting light to the object is situated as one unit with the imaging device. A background-illumination device for emitting light to the object is situated below the object. An image obtained by the imaging device is stored in a memory unit of an image processing apparatus. The image processing apparatus includes a processing unit for logically processing the image. The illumination devices are connected to power supplies. The image processing apparatus and the power supplies are controlled by a controller. Thus, a bonding position is recognized easily with simple structure, the reliability of test results is enhanced, and the cost for testing is reduced by a decrease in the processing time.Type: GrantFiled: October 4, 1995Date of Patent: April 28, 1998Assignee: Kabushiki Kaisha ToshibaInventor: Yuichi Miyahara
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Patent number: 5170062Abstract: A wire bonding inspecting apparatus for inspecting wires bonded between a semiconductor chip and leads comprises an imaging device for optically taking an image of the wire and converting the optical image into electric image signals; a moving device for moving the imaging device; an image processing inspecting unit for obtaining wire positional coordinates on the basis of image signals and inspecting the wire on the basis of the positional coordinates; and a main controller.Type: GrantFiled: October 11, 1991Date of Patent: December 8, 1992Assignee: Kabushiki Kaisha ToshibaInventor: Yuichi Miyahara
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Patent number: 5156319Abstract: Wire bonding inspection equipment includes a judging unit for judging whether or not wire bonding of a semiconductor device is acceptabe and for producing a defect signal when the semiconductor device is judged to be defective. In response to the defect signal wires of the defective semiconductor device are broken by a breaking unit, and a defect mark is applied on the defective semiconductor device by a defective mark putting unit in response to the defect signal, the defect mark applying unit applying the defect mark on an area other than an area to be covered with sealing material.Type: GrantFiled: September 12, 1991Date of Patent: October 20, 1992Assignee: Kabushiki Kaisha ToshibaInventors: Mitsusada Shibasaka, Yuichi Miyahara
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Patent number: 5085534Abstract: This invention relates to a mechanical pencil capable of utilizing effectively a writing lead and having an improved lead protection pipe. A protuberance having a surface having a hardness equal to, or higher than, that of a lead is formed on the inner surface of the lead protection pipe by dispersing and depositing powder; very small coil-like fibers having a surface having hardness equal to, or higher than, that of the lead are dispersed and deposited on the inner surface of the lead protection pipe through a base material; an inorganic film having a protuberance having hardness equal to, or higher than, that of the lead is formed on the inner surface of the lead protection pipe; or a ring-like lead retaining member is disposed inside the lead protection pipe. The lead retaining member has a treated portion having a surface having hardness equal to, or higher than, that of the lead, and a partial play relative to the inner surface of the lead protection pipe.Type: GrantFiled: October 4, 1990Date of Patent: February 4, 1992Assignee: Pentel Kabushiki KaishaInventors: Kamakura Kenichi, Nobuo Murasawa, Tsukasa Sasaki, Yuichi Miyahara, Hiroaki Okabayashi, Tetsuya Sugiyama, Masamitsu Nagahama, Tsuruo Nakayama