Abstract: A semiconductor device having a capacitor formed in a multilayer wiring structure, the semiconductor device comprising a multilayer wiring structure including a plurality of wiring layers formed on a substrate, a capacitor arranged in a predetermined wiring layer in the multilayer wiring structure and having a lower electrode, a dielectric film, and an upper electrode, a first via formed in the predetermined wiring layer and connected to a top surface of the upper electrode of the capacitor, and a second via formed in an overlying wiring layer stacked on the predetermined wiring layer, the second via being formed on the first via.

Abstract: There is disclosed a semiconductor device comprising at least one first insulating film provided above a substrate, being formed with at least one first recess having a first width, and being formed with at least one second recess having a second width which is 1/x (x: positive numbers larger than 1) a size of the first width and having a same depth as the first recess, a second insulating film provided at both sides of the first recess and at a lower part of the second recess, and a conductor provided inside of the second insulating films provided at the both sides of the first recess with extending from an opening of the first recess to a bottom surface thereof, and provided with extending from an opening of the second recess to an upper surface of the second insulating film provided at the lower part of the second recess.

Abstract: A semiconductor device having a capacitor formed in a multilayer wiring structure, the semiconductor device comprising a multilayer wiring structure including a plurality of wiring layers formed on a substrate, a capacitor arranged in a predetermined wiring layer in the multilayer wiring structure and having a lower electrode, a dielectric film, and an upper electrode, a first via formed in the predetermined wiring layer and connected to a top surface of the upper electrode of the capacitor, and a second via formed in an overlying wiring layer stacked on the predetermined wiring layer, the second via being formed on the first via.

Abstract: There is disclosed a semiconductor device comprising at least one first insulating film provided above a substrate, being formed with at least one first recess having a first width, and being formed with at least one second recess having a second width which is 1/x (x: positive numbers larger than 1) a size of the first width and having a same depth as the first recess, a second insulating film provided at both sides of the first recess and at a lower part of the second recess, and a conductor provided inside of the second insulating films provided at the both sides of the first recess with extending from an opening of the first recess to a bottom surface thereof, and provided with extending from an opening of the second recess to an upper surface of the second insulating film provided at the lower part of the second recess.

Abstract: There is here disclosed a semiconductor device comprising a capacitor provided on a substrate and formed by sandwiching a capacitive insulating film between lower and upper electrodes, an interlayer insulating film of an n-th layer (n is 1 or greater integer) provided on the substrate to cover the capacitor, and a plurality of plugs and a plurality of wirings provided on the substrate, wherein an electrode wiring among the wirings which is electrically connected to the lower or upper electrode above the capacitor is provided in an interlayer insulating film of an (n+1)-th layer or more formed on the interlayer insulating film of the n-th layer.

Abstract: A process of manufacturing a semiconductor device. The initial process steps are forming a first insulating film above a semiconductor substrate and removing a selected portion of the first insulating film to form an opening. The next step is depositing a first electrode, a dielectric film and a second electrode successively on a bottom portion of the opening, The deposits being oriented such that they are in substantially parallel relationship with a surface of the semiconductor substrate. The final steps are removing selected portions of the first electrode, the dielectric film and the second electrode, forming a capacitor at a selected position in the opening, forming a second insulating film at least in the opening, and forming a third insulating film on the second insulating film.

Abstract: There is here disclosed a semiconductor device comprising a capacitor provided on a substrate and formed by sandwiching a capacitive insulating film between lower and upper electrodes, an interlayer insulating film of an n-th layer (n is 1 or greater integer) provided on the substrate to cover the capacitor, and a plurality of plugs and a plurality of wirings provided on the substrate, wherein an electrode wiring among the wirings which is electrically connected to the lower or upper electrode above the capacitor is provided in an interlayer insulating film of an (n+1)-th layer or more formed on the interlayer insulating film of the n-th layer.

Abstract: A semiconductor device having a capacitor formed in a multilayer wiring structure, the semiconductor device comprising a multilayer wiring structure including a plurality of wiring layers formed on a substrate, a capacitor arranged in a predetermined wiring layer in the multilayer wiring structure and having a lower electrode, a dielectric film, and an upper electrode, a first via formed in the predetermined wiring layer and connected to a top surface of the upper electrode of the capacitor, and a second via formed in an overlying wiring layer stacked on the predetermined wiring layer, the second via being formed on the first via.

Abstract: A semiconductor device includes a first insulating film comprising an opening, a capacitor formed at a selected position in the opening, a second insulating film formed at least in the opening, and a third insulating film formed on the second insulating film.

Abstract: A semiconductor device includes a first insulating film comprising an opening, a capacitor formed at a selected position in the opening, a second insulating film formed at least in the opening, and a third insulating film formed on the second insulating film.

Abstract: A semiconductor device includes a first insulating film comprising an opening, a capacitor formed at a selected position in the opening, a second insulating film formed at least in the opening, and a third insulating film formed on the second insulating film.

Abstract: In a semiconductor device, a first conductive film made of, for example, polysilicon is formed on the element region of the semiconductor substrate. An insulation film is formed on the semiconductor substrate, for covering at least the first conductive film. A second conductive film covers at least the end portion of the insulation film. The first conductive film is used as a gate electrode of the MOS transistor, and the second conductive film is used as a protection film for covering and protecting the end portion of the insulation film and a lead-out electrode of the bipolar transistor. The end portion of the insulation film is covered and protected by the second conductive film obtained by patterning the conductive layer made of, for example, polysilicon. Further, the conductive layer is patterned so that stepped portions formed on the insulation film and the end portion of the insulation film are covered, and using this pattern, anisotropic etching is carried out.

Abstract: The present invention provides a method of manufacturing a semiconductor device to prevent the generation of crystalline defects due to shorting between interconnects resulting from etch residue as a result of the generation of vertical bird's beaks on top of the trench during field oxidation layer formation. The method includes forming an epitaxial layer over a semiconductor substrate, depositing a first SiO.sub.2 layer, an SiN layer and a second SiO.sub.2 layer in that order upon said epitaxial layer and forming a trench from the second SiO.sub.2 layer extending into the semiconductor substrate. A third SiO.sub.2 layer is formed coating said trench with a region of said third Si0.sub.2 layer removed adjacent to said first SiO.sub.2 layer to expose a portion of said epitaxial layer within said trench. The trench is then filled with a first polysilicon layer to coat the third SiO.sub.2 layer and the first SiO.sub.2 layer followed by removal of the second SiO.sub.

Abstract: In a semiconductor device, a first conductive film made of, for example, polysilicon is formed on the element region of the semiconductor substrate. An insulation film is formed on the semiconductor substrate, for covering at least the first conductive film. A second conductive film covers at least the end portion of the insulation film. The first conductive film is used as a gate electrode of the MOS transistor, and the second conductive film is used as a protection film for covering and protecting the end portion of the insulation film and a lead-out electrode of the bipolar transistor. The end portion of the insulation film is covered and protected by the second conductive film obtained by patterning the conductive layer made of, for example, polysilicon. Further, the conductive layer is patterned so that stepped portions formed on the insulation film and the end portion of the insulation film are covered, and using this pattern, anisotropic etching is carried out.

Abstract: A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layer disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

Abstract: A resin sealed semiconductor device for use in testing is disclosed, in which a first MOS field effect transistor is formed in a region within 100 .mu.m from an outer perimeter of a main surface of a silicon substrate, and a second MOS field effect transistor is formed in a region 100 .mu.m or more distant from an outer perimeter of the main surface, and the first and second MOS field effect transistors are encapsulated with resin. Dimensions and materials of the first MOS field effect transistor and the second MOS field effect transistor are identical. By comparing the electric characteristics of the first MOS field effect transistor and the electric characteristics of the second MOS field effect transistor, the effect produced on the MOS field effect transistors by the mechanical stresses due to the resin seal applied from a side direction of silicon substrate can be evaluated.

Abstract: A resin sealed semiconductor device includes a semiconductor chip formed on a substrate and sealed with resin. A concave portion is formed on a major surface of a semiconductor substrate between an insulating film for isolation and an edge of the major surface of the semiconductor substrate. This concave portion is filled with a buffer member having an elastic modulus smaller than that of the material of the semiconductor substrate. Mechanical stress applied to an edge of the semiconductor substrate, caused by the callosity of resin, is absorbed and reduced by the buffer member. A portion of the semiconductor substrate between the concave portion and the insulating film for isolation prevents the remainder of the mechanical stress from being transmitted from the buffer member to the insulating film and circuit elements.

Abstract: A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layers disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

Abstract: In a content addressable memory (CAM) cell according to the present invention, a pair of non-volatile memory transistors hold data, whereby stored data will not disappear even if power is cut. Conducting terminals of these non-volatile transistors are connected to a bit line pair, so that the stored data can be directly read out from the bit line pair. Further, the invention CAM system converts the value of a current flowing in a match line into a voltage value to perform content reference, and hence the same can be employed as an associative memory system.