Patents by Inventor Yuichi Nakayoshi
Yuichi Nakayoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9073173Abstract: A polishing pad shape measured by a polishing pad shape measuring apparatus is modified into a target shape of a polishing pad by using a dressing tool so that a wafer has a desired surface shape. The invention is a method for shape modification of a polishing pad 14 for polishing a workpiece into a desired surface shape, comprising: a measurement step S9 of measuring a polishing pad shape in a state of being attached to a plate 12 by using a polishing pad shape measuring apparatus 10; a condition determination step S10 of selecting a dressing recipe capable of polishing the workpiece into a desired surface shape from a plurality of pre-provided dressing recipes based on the measurement result in the measurement step S9; and a shape modification step S11 of dressing the polishing pad 14 by using the dressing recipe determined in the condition determination step S10.Type: GrantFiled: December 29, 2010Date of Patent: July 7, 2015Assignee: SUMCO CorporationInventors: Hiroshi Takai, Yuichi Nakayoshi
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Patent number: 8728942Abstract: Mirror-polishing a front surface of a silicon wafer using polishing liquid composed of an abrasive grain-free alkaline solution including water-soluble polymers simplifies a polishing process, thus leading to an increase in productivity and a reduction in cost, and reduces the density of LPDs attributable to processing and occurring in the front surface of a mirror-polished wafer, thus improving the surface roughness of the wafer front surface.Type: GrantFiled: August 20, 2010Date of Patent: May 20, 2014Assignee: Sumico CorporationInventors: Shinichi Ogata, Kazushige Takaishi, Hironori Nishimura, Shigeru Okuuchi, Shunsuke Mikuriya, Yuichi Nakayoshi
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Patent number: 8545712Abstract: In a method of manufacturing semiconductor wafers, front and back surfaces of the semiconductor wafers are simultaneously polished with a double-side polishing machine that includes: a carrier for accommodating the semiconductor wafer; and an upper press platen and a lower press platen for sandwiching the carrier. The method includes: accommodating the semiconductor wafer in the carrier while a thickness of the semiconductor wafer is set to be larger than a thickness of the carrier by 0 ?m to 5 ?m; and polishing the semiconductor wafer while feeding a polishing slurry to between the surfaces of the semiconductor wafer and surfaces of the press platens. In the polishing, an allowance of both surfaces of the semiconductor wafer is set at 5 ?m or less in total.Type: GrantFiled: September 11, 2008Date of Patent: October 1, 2013Assignee: Sumco Techxiv CorporationInventors: Hiroshi Takai, Kenji Satomura, Yuichi Nakayoshi, Katsutoshi Yamamoto, Kouji Mizowaki
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Patent number: 8296961Abstract: A polishing pad thickness measuring method measures the thickness of a polishing pad attached to an upper surface of a surface plate. The polishing pad thickness measuring method measures a first distance between an upper surface of the polishing pad and a reference position on a vertical line perpendicular to the surface of the polishing pad and a second distance between an upper surface of the surface plate and the reference position on the vertical line, and calculates the thickness of the polishing pad from the difference between the first and second distances.Type: GrantFiled: January 27, 2010Date of Patent: October 30, 2012Assignee: Sumco CorporationInventors: Yuichi Nakayoshi, Hiroshi Takai, Hironori Nishimura
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Publication number: 20120156878Abstract: Mirror-polishing a front surface of a silicon wafer using polishing liquid composed of an abrasive grain-free alkaline solution including water-soluble polymers simplifies a polishing process, thus leading to an increase in productivity and a reduction in cost, and reduces the density of LPDs attributable to processing and occurring in the front surface of a mirror-polished wafer, thus improving the surface roughness of the wafer front surface.Type: ApplicationFiled: August 20, 2010Publication date: June 21, 2012Applicant: SUMCO CORPORATIONInventors: Shinichi Ogata, Kazushige Takaishi, Hironori Nishimura, Shigeru Okuuchi, Shunsuke Mikuriya, Yuichi Nakayoshi
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Publication number: 20120149177Abstract: An object of the invention is to provide an epitaxial silicon wafer in higher quality with good flatness and thickness uniformity. The object is achieved by a method characterized in that after an epitaxial film 20 is formed on a surface of a mirror polished silicon wafer 10, a grinding process, a polishing process, or a chemical etching process is performed only on the rear surface of the silicon wafer 10, and silicon precipitate 21 that adheres to an end portion of the rear surface of the silicon wafer 10 in the formation of the epitaxial film 20 is removed.Type: ApplicationFiled: August 6, 2010Publication date: June 14, 2012Inventors: Yuichi Nakayoshi, Hironori Nishimura
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Publication number: 20110171885Abstract: A polishing pad shape measured by a polishing pad shape measuring apparatus is modified into a target shape of a polishing pad by using a dressing tool so that a wafer has a desired surface shape. The invention is a method for shape modification of a polishing pad 14 for polishing a workpiece into a desired surface shape, comprising: a measurement step S9 of measuring a polishing pad shape in a state of being attached to a plate 12 by using a polishing pad shape measuring apparatus 10; a condition determination step S10 of selecting a dressing recipe capable of polishing the workpiece into a desired surface shape from a plurality of pre-provided dressing recipes based on the measurement result in the measurement step S9; and a shape modification step S11 of dressing the polishing pad 14 by using the dressing recipe determined in the condition determination step S10.Type: ApplicationFiled: December 29, 2010Publication date: July 14, 2011Applicant: SUMCO CORPORATIONInventors: Hiroshi Takai, Yuichi Nakayoshi
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Publication number: 20100285665Abstract: In a method of manufacturing semiconductor wafers, front and hack surfaces of the semiconductor wafers are simultaneously polished with a double-side polishing machine that includes: a carrier for accommodating the semiconductor wafer; and an upper press platen and a lower press platen for sandwiching the carrier. The method includes: accommodating the semiconductor wafer in the carrier while a thickness of the semiconductor wafer is set to be larger than a thickness of the carrier by 0 ?m to 5 ?m; and polishing the semiconductor wafer while feeding a polishing slurry to between the surfaces of the semiconductor wafer and surfaces of the press platens. In the polishing, an allowance of both surfaces of the semiconductor wafer is set at 5 ?m or less in total.Type: ApplicationFiled: September 11, 2008Publication date: November 11, 2010Applicant: SUMCO TECHXIV CORPORATIONInventors: Hiroshi Takai, Kenji Satomura, Yuichi Nakayoshi, Katsutoshi Yamamoto, Kouji Mizowaki
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Publication number: 20100197197Abstract: A polishing pad thickness measuring method measures the thickness of a polishing pad attached to an upper surface of a surface plate. The polishing pad thickness measuring method measures a first distance between an upper surface of the polishing pad and a reference position on a vertical line perpendicular to the surface of the polishing pad and a second distance between an upper surface of the surface plate and the reference position on the vertical line, and calculates the thickness of the polishing pad from the difference between the first and second distances.Type: ApplicationFiled: January 27, 2010Publication date: August 5, 2010Applicant: SUMCO CORPORATIONInventors: Yuichi NAKAYOSHI, Hiroshi TAKAI, Hironori NISHIMURA
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Patent number: 6517667Abstract: An polishing apparatus consists of a piston which is fixed to the rotation axis, a ceramic plate which is oppositely arranged against the piston via a silicone gel, and a cylinder which houses these components. The wafer is attached on the bottom surface of a backing pad, and will be pressed and rotated by the piston in order to polish the surface thereof.Type: GrantFiled: June 17, 1998Date of Patent: February 11, 2003Assignee: Komatsu Electronic Metals Co., Ltd.Inventor: Yuichi Nakayoshi
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Patent number: 6495465Abstract: The present invention provides a method for appraising the condition of a polishing cloth, and a method for manufacturing semiconductor wafers employing the disclosed appraisal method, allowing acceptably low light point defect numbers of semiconductor wafers to be maintained. The disclosed method comprises polishing the semiconductor wafer using a polishing cloth, washing the wafer, and drying the wafer. The size of particles comprising light point defects is chosen, and the number of light point defects on the semiconductor wafer is counted. Typically, the diameter of particles comprising light point defects is set as 0.12 &mgr;m or greater. The polishing cloth is exchanged when the number of light point defects counted exceeds a prescribed number.Type: GrantFiled: March 10, 1999Date of Patent: December 17, 2002Assignee: Komatsu Electronic Metals Co., Ltd.Inventors: Yuichi Nakayoshi, Naoki Yamada
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Publication number: 20010026948Abstract: The present invention provides a method for appraising the condition of a polishing cloth, and a method for manufacturing semiconductor wafers employing the disclosed appraisal method, allowing acceptably low light point defect numbers of semiconductor wafers to be maintained. The disclosed method comprises polishing the semiconductor wafer using a polishing cloth, washing the wafer, and drying the wafer. The size of particles comprising light point defects is chosen, and the number of light point defects on the semiconductor wafer is counted. Typically, the diameter of particles comprising light point defects is set as 0.12 &mgr;m or greater. The polishing cloth is exchanged when the number of light point defects counted exceeds a prescribed number.Type: ApplicationFiled: March 10, 1999Publication date: October 4, 2001Inventors: YUICHI NAKAYOSHI, NAOKI YAMADA
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Patent number: 6090688Abstract: A method for fabricating an SOI substrate is provided, which has an active substrate formed as a thin film. The method comprises the steps of: using a both-side polishing apparatus to polish both sides of a supporting substrate 1; bonding an active substrate 2 onto the supporting substrate 1. to form a bonded-wafer; removing an unbonded portion formed at the circumference of the bonded-wafer; flat grinding the active substrate 2 to reduce the thickness thereof; etching the active substrate 2 by spin etching; and processing the active substrate to be a thin film by PACE processing.Type: GrantFiled: November 15, 1996Date of Patent: July 18, 2000Assignee: Komatsu Electronic Metals Co., Ltd.Inventors: Tadashi Ogawa, Akihiro Ishii, Yuichi Nakayoshi
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Patent number: 6004860Abstract: An SOI substrate and a method for fabricating the same are provided to sharpen the departing angle at the circumference of the active substrate, and provide the active substrate with a uniform thickness. An attached wafer of the present invention is formed by processing the upper side of the base substrate so that its thickness increases from the center to the circumference, and attaching the active substrate to the processed side of the base substrate. The unattached portion of the attached wafer is removed. Then mirror processing is performed to provide the active substrate with a substantially uniform thickness along the processed side of the base substrate.Type: GrantFiled: August 30, 1996Date of Patent: December 21, 1999Assignee: Komatsu Electronic Metals Co., Ltd.Inventors: Tadashi Ogawa, Akihiro Ishii, Yuichi Nakayoshi
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Patent number: 6001007Abstract: A backing pad 7 is secured on the bottom of a ceramic plate 6. A template 1 is secured on the bottom of the backing pad 7. The thickness of the template 1 successively diminishes from the inner periphery wall 12 of the central accommodation opening for restraining the semiconductor wafer, toward the outer periphery wall 13 of the template 1, so that the bottom of the template 1 is inclined and the cross section of the template 1 is tapered.Type: GrantFiled: May 30, 1997Date of Patent: December 14, 1999Assignee: Komatsu Electronic Metals Co., Ltd.Inventors: Masahiko Maeda, Yuichi Nakayoshi
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Patent number: 5893755Abstract: A method of polishing semiconductor wafers is provided. The method will not impair the original (pre-polishing) contour of semiconductor wafers, and semiconductor wafers can be polished so as to have high flatness. In the method according to this invention, a silicon rubber sheet 2 is fixed on a base 4, and an abrasive cloth 5 is secured on the silicon rubber sheet 2. A template 1 of thickness close to that of a semiconductor wafer 10 is secured on a backing pad 32. The semiconductor wafer 10 is restrained by the template 1 and is impelled in to contact with the abrasive cloth 5 to polish effectively.Type: GrantFiled: May 30, 1997Date of Patent: April 13, 1999Assignee: Komatsu Electronic Metals Co., Ltd.Inventor: Yuichi Nakayoshi
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Patent number: 5863829Abstract: The present invention provides a process for fabricating an SOI substrate with no peripheral scratches and with enhanced fabrication efficiency. The present process includes bonding a semiconductor wafer of an active substrate 1 and a semiconductor base wafer 2 to form a bonded wafer 4; surface-grinding the active substrate 1; spin etching the surface-ground active substrate 1; and PACE processing the etched active substrate 1 to form the active substrate into a thin film and simultaneously, to remove the non-bonded peripheral portion of the bonded wafer 4.Type: GrantFiled: November 13, 1996Date of Patent: January 26, 1999Assignee: Komatsu Electronic Metals Co., Ltd.Inventors: Yuichi Nakayoshi, Hiroaki Yamamoto, Akihiro Ishii