Abstract: The technique of the present disclosure has an object to perform PWM control of DC motors with a CPU and a motor drive circuit connected by a smaller number of serial interfaces, and provides a motor drive circuit comprising: energization control units to switch the directions of energization of motors by using switching elements to be driven by PWM signals; a reception unit to receive data indicating energization of the motor and the duty ratio of the PWM signal for each energization control unit from a computation apparatus by serial communication; a first signal generation unit to generate a motor control signal for controlling energization of the motor and the duty ratio based on the data for each energization control unit; and a second signal generation unit to generate the PWM signal having the duty ratio set according to the corresponding motor control signal for each energization control unit.

Abstract: The technique of the present disclosure has an object to perform PWM control of DC motors with a CPU and a motor drive circuit connected by a smaller number of serial interfaces, and provides a motor drive circuit comprising: energization control units to switch the directions of energization of motors by using switching elements to be driven by PWM signals; a reception unit to receive data indicating energization of the motor and the duty ratio of the PWM signal for each energization control unit from a computation apparatus by serial communication; a first signal generation unit to generate a motor control signal for controlling energization of the motor and the duty ratio based on the data for each energization control unit; and a second signal generation unit to generate the PWM signal having the duty ratio set according to the corresponding motor control signal for each energization control unit.

Abstract: A signal line used in a key matrix is shared between a signal line used in a first display unit and a signal line used in a second display unit. Two types of periodical pulse signals are superimposed on a level signal which indicates data displayed on the second display unit. One type is a pulse signal for detecting key input and another type is a pulse signal which indicates data displayed on the first display unit.

Abstract: An apparatus which has a load that consumes a predetermined amount of electric power per unit time includes a power source circuit configured to generate a voltage for driving the load, a capacitor which is connected to a supply line for supplying electric power to the load from the power source circuit and configured to stabilize a potential of the load, a first supply circuit which can supply electric power smaller than the predetermined amount to the capacitor and can discharge a charge from the capacitor, a second supply circuit which can supply electric power larger than the predetermined amount to the capacitor, a switch circuit configured to operate each of the first supply circuit and the second supply circuit, and a holding circuit configured to hold information based on the operation of the first supply circuit.

Abstract: A signal line used in a key matrix is shared between a signal line used in a first display unit and a signal line used in a second display unit. Two types of periodical pulse signals are superimposed on a level signal which indicates data displayed on the second display unit. One type is a pulse signal for detecting key input and another type is a pulse signal which indicates data displayed on the first display unit.

Abstract: A signal line used in a key matrix is shared between a signal line used in a first display unit and a signal line used in a second display unit. Two types of periodical pulse signals are superimposed on a level signal which indicates data displayed on the second display unit. One type is a pulse signal for detecting key input and another type is a pulse signal which indicates data displayed on the first display unit.

Abstract: An apparatus which has a load that consumes a predetermined amount of electric power per unit time includes a power source circuit configured to generate a voltage for driving the load, a capacitor which is connected to a supply line for supplying electric power to the load from the power source circuit and configured to stabilize a potential of the load, a first supply circuit which can supply electric power smaller than the predetermined amount to the capacitor and can discharge a charge from the capacitor, a second supply circuit which can supply electric power larger than the predetermined amount to the capacitor, a switch circuit configured to operate each of the first supply circuit and the second supply circuit, and a holding circuit configured to hold information based on the operation of the first supply circuit.

Abstract: To provide an image processing technique compatible with both a CCD and a CIS, which controls storage of image data read by each device in a memory and the read of the stored data for each rectangular area to obtain a high memory efficiency, an image processing apparatus includes an input section which executes input processing of image data read by an image reading device in accordance with the data output format of the device, an output data control section which distributes the image data that has undergone the input processing by the input section in accordance with the output format of the image reading device, an address generation section which generates address information corresponding to the output format to store the distributed image data in a memory, and a memory control section which DMA-transfers the distributed image data to the memory and stores the image data on the basis of the generated address information.

Abstract: To provide an image processing technique compatible with both a CCD and a CIS, which controls storage of image data read by each device in a memory and the read of the stored data for each rectangular area to obtain a high memory efficiency, an image processing apparatus includes a memory area control section which sets, for image data bitmapped on a first memory, a rectangular area divided in a main scanning direction and sub-scanning direction, an address generation section which generates address information to read out image data corresponding to the rectangular area in correspondence with the set rectangular area, a memory control section which reads out the image data corresponding to the rectangular area and DMA-transfers the image data to a second memory in accordance with the generated address information, and an image processing section which executes image processing for each rectangular area of the DMA-transferred data by using the second memory.

Abstract: To provide an image processing technique compatible with both a CCD and a CIS, which controls storage of image data read by each device in a memory and the read of the stored data for each rectangular area to obtain a high memory efficiency, an image processing apparatus includes a memory area control section which sets, for image data bitmapped on a first memory, a rectangular area divided in a main scanning direction and sub-scanning direction, an address generation section which generates address information to read out image data corresponding to the rectangular area in correspondence with the set rectangular area, a memory control section which reads out the image data corresponding to the rectangular area and DMA-transfers the image data to a second memory in accordance with the generated address information, and an image processing section which executes image processing for each rectangular area of the DMA-transferred data by using the second memory.

Abstract: A signal line used in a key matrix is shared between a signal line used in a first display unit and a signal line used in a second display unit. Two types of periodical pulse signals are superimposed on a level signal which indicates data displayed on the second display unit. One type is a pulse signal for detecting key input and another type is a pulse signal which indicates data displayed on the first display unit.

Abstract: To provide an image processing technique compatible with both a CCD and a CIS, which controls storage of image data read by each device in a memory and the read of the stored data for each rectangular area to obtain a high memory efficiency, an image processing apparatus includes a memory area control section which sets, for image data bitmapped on a first memory, a rectangular area divided in a main scanning direction and sub-scanning direction, an address generation section which generates address information to read out image data corresponding to the rectangular area in correspondence with the set rectangular area, a memory control section which reads out the image data corresponding to the rectangular area and DMA-transfers the image data to a second memory in accordance with the generated address information, and an image processing section which executes image processing for each rectangular area of the DMA-transferred data by using the second memory.

Abstract: A low power dissipation facsimile apparatus is capable of accommodating a plurality of lines. This apparatus is arranged to reduce the power consumption still more. The apparatus comprises a first control unit having a low power dissipation mode, which controls a first line and the entire body of the facsimile apparatus, and a second control unit having a low dissipation mode, wherein controls a second line and transfers communication data to the first control unit. Then, for the reception only on the first line, and also, for the transmission and the copying operation, the first control unit rises from the low power dissipation mode to execute operation accordingly.

Abstract: To provide an image processing technique compatible with both a CCD and a CIS, which controls storage of image data read by each device in a memory and the read of the stored data for each rectangular area to obtain a high memory efficiency, an image processing apparatus includes an input section which executes input processing of image data read by an image reading device in accordance with the data output format of the device, an output data control section which distributes the image data that has undergone the input processing by the input section in accordance with the output format of the image reading device, an address generation section which generates address information corresponding to the output format to store the distributed image data in a memory, and a memory control section which DMA-transfers the distributed image data to the memory and stores the image data on the basis of the generated address information.

Abstract: To provide an image processing technique compatible with both a CCD and a CIS, which controls storage of image data read by each device in a memory and the read of the stored data for each rectangular area to obtain a high memory efficiency, an image processing apparatus includes a memory area control section which sets, for image data bitmapped on a first memory, a rectangular area divided in a main scanning direction and sub-scanning direction, an address generation section which generates address information to read out image data corresponding to the rectangular area in correspondence with the set rectangular area, a memory control section which reads out the image data corresponding to the rectangular area and DMA-transfers the image data to a second memory in accordance with the generated address information, and an image processing section which executes image processing for each rectangular area of the DMA-transferred data by using the second memory.