Patents by Inventor Yuichi Nasu

Yuichi Nasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8530801
    Abstract: A method and an apparatus for manufacturing a semiconductor wafer are provided for improving a quality of the semiconductor wafer, and further, for improving a quality of a semiconductor device manufactured by using the semiconductor wafer, by preventing warping from being generated at a stage of a placing step, at the time of performing heat treatment to a semiconductor wafer substrate. The placing process is performed by a placing means so that a time when a temperature difference between a wafer front surface temperature and a wafer rear surface temperature becomes maximum, and a time when warping is generated in the wafer are prior to a time when the wafer is brought into contact with lift pins or a susceptor (i.e., a time after the temperature is at an upper limit value of an infrared temperature region at 600° C.), and the lift pins are brought into contact with the wafer rear surface.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: September 10, 2013
    Assignee: Sumco Techxiv Kabushiki Kaisha
    Inventors: Yuichi Nasu, Hirotaka Katou, Kazuhiro Narahara, Hideyuki Matsunaga
  • Publication number: 20090226293
    Abstract: A method and an apparatus for manufacturing a semiconductor wafer are provided for improving a quality of the semiconductor wafer, and further, for improving a quality of a semiconductor device manufactured by using the semiconductor wafer, by preventing warping from being generated at a stage of a placing step, at the time of performing heat treatment to a semiconductor wafer substrate. The placing process is performed by a placing means so that a time when a temperature difference between a wafer front surface temperature and a wafer rear surface temperature becomes maximum, and a time when warping is generated in the wafer are prior to a time when the wafer is brought into contact with lift pins or a susceptor (i.e., a time after the temperature is at an upper limit value of an infrared temperature region at 600° C.), and the lift pins are brought into contact with the wafer rear surface.
    Type: Application
    Filed: June 30, 2006
    Publication date: September 10, 2009
    Applicant: SUMCO TECHXIV KABUSHIKI KAISHA
    Inventors: Yuichi Nasu, Hirotaka Katou, Kazuhiro Narahara, Hideyuki Matsunaga
  • Patent number: 7537658
    Abstract: An oxide film 13 on the surface of the substrate 11 and an inner wall oxide film 112 in a COP 111 exposed to the surface of the substrate 11 are removed by cleaning the surface of the substrate 11 with a hydrofluoric acid solution. The substrate 11 is then cleaned with ozone water, thereby forming an oxide film 13 on the surface of the substrate 11. Thereafter the substrate 11 is subjected to a heat treatment for removing the oxide film 13 on the surface of the substrate 11. Consequently, the COP 111 on the surface of the substrate 11 is planarized to be eliminated from the substrate surface. Thereafter an epitaxial layer 12 is formed on the surface of the substrate 11.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: May 26, 2009
    Assignee: Sumco Techxiv Corporation
    Inventors: Yuichi Nasu, Kazuhiro Narahara
  • Publication number: 20080131605
    Abstract: An oxide film 13 on the surface of the substrate 11 and an inner wall oxide film 112 in a COP 111 exposed to the surface of the substrate 11 are removed by cleaning the surface of the substrate 11 with a hydrofluoric acid solution. The substrate 11 is then cleaned with ozone water, thereby forming an oxide film 13 on the surface of the substrate 11. Thereafter the substrate 11 is subjected to a heat treatment for removing the oxide film 13 on the surface of the substrate 11. Consequently, the COP 111 on the surface of the substrate 11 is planarized to be eliminated from the substrate surface. Thereafter an epitaxial layer 12 is formed on the surface of the substrate 11.
    Type: Application
    Filed: December 20, 2005
    Publication date: June 5, 2008
    Applicant: SUMCO TECHXIV CORPORATION
    Inventors: Yuichi Nasu, Kazuhiro Narahara