Abstract: According to one embodiment, an information processing device is provided with a memory, a plurality of processors, a router group, and an address protection unit. The plurality of the processors generate memory access packets each of which defines memory access requests for the memory, the memory access packet including an access destination address and an access type. The router group is provide with first routers which are connected to the memory and second routers which form transfer paths between the first router and the plurality of the processors, and transmits the memory access packets generated by the plurality of the processors to the memory. The address protection unit examines the memory access packets which pass through the first routers to detect a violated memory access.

Abstract: A debugging device configured to debug a program includes an analysis section configured to analyze information of a code that does not need to be debugged in which a predetermined processing instruction is described, the code being generated by optimization of a compiler for a source code of the program, and an output section configured to output processing content information, a start address, and an end address of the code that does not need to be debugged which are obtained by the analysis.

Abstract: To provide an inexpensive lead component which can be easily connected to a semiconductor chip and which has satisfactory connectability. There is provided a lead component including a base material having a connection part for connecting to a semiconductor chip, comprising: a solder part having a Zn layer made of a Zn-bonding material rolled and clad-bonded on the base material, and an Al layer made of an Al-bonding material rolled and clad-bonded on the Zn layer, in a prescribed region including the connection part on the base material; and the solder part further comprising a metal thin film composed of one kind or two kinds or more of Au, Ag, Cu, Ni, Pd, and Pt covering a surface of the Al layer.

Abstract: An image display apparatus including a first storage means for storing at least one item of image data, correction condition data for correcting the image data, and corrected image data obtained after the image data is corrected on the basis of the correction condition data; an image processing means for producing the corrected image data; a display means comprising a screen for superimposing an original image based on the image data and a corrected image based on the corrected image data onto each other and displaying either the original image or the corrected image; an input means for selecting an image to be displayed on the display screen, and a display control means for switching between the images in response to an input from the input means, so that either the original image or the corrected image is displayed on the display screen.

Abstract: The present invention is directed at obtaining a high yield of a target substance and simultaneously securing high productivity. A reaction apparatus 10 has: a main flow channel 12 having an inner diameter of 3 mm, in which a raw material M1 flows; an introduction flow channel 14 in which a raw material M2 that causes a chemical reaction with the raw material M1 flows; and five branch introduction flow channels 16a to 16e which are branched from the introduction flow channel 14 and introduce the raw material M2 to the main flow channel 12, at predetermined introduction points 12o to 12s in the main flow channel 12. Here, in the main flow channel 12, the flow channel lengths of the flow channels 12b to 12d between adjacent introduction points 12p to 12s are not longer than those of the flow channels 12a to 12c between the next previous adjacent introduction points 12o to 12r in a flow direction of the raw material M1.

Abstract: First tag addresses and data are stored in association with first index addresses in a memory cell unit provided in a cache memory. The first tag addresses and the first index addresses are configured based on address information respectively. Designation address information is provided to designate an address to read one of the stored data. The designation address information is converted to a second index address and second tag address by an address converter, in order to read the one of the stored data according to the designation address information. The memory cell unit is accessed according to the obtained second index address. When one of the first tag addresses matches the second tag address, the one of the data corresponding to the one of the first tag addresses is read. The designation address information and the one of the data are displayed in a cache memory display unit.

Abstract: A debugging device configured to debug a program includes an analysis section configured to analyze information of a code that does not need to be debugged in which a predetermined processing instruction is described, the code being generated by optimization of a compiler for a source code of the program, and an output section configured to output processing content information, a start address, and an end address of the code that does not need to be debugged which are obtained by the analysis.

Abstract: According to the present invention, there is provided a debug support apparatus having, a decoder configured to receive an instruction output from a compiler which receives a source code, decode the instruction, and output a decoding result; and a display unit configured to receive debug information output from the compiler and the decoding result output from the decoder and display at least a correspondence between each decoded instruction and a position in the source code.