Abstract: A semiconductor device includes a stripe-shaped gate trench formed in one major surface of n-type drift layer, a gate trench including gate polysilicon formed therein, and a gate polysilicon connected to a gate electrode. A p-type base layer is formed selectively in mesa region between adjacent gate trenches and a p-type base layer including an n-type emitter layer and connected to emitter electrode. One or more dummy trenches are formed between p-type base layers adjoining to each other in the extending direction of gate trenches. An electrically conductive dummy polysilicon is formed on an inner side wall of dummy trench with a gate oxide film interposed between the dummy polysilicon and dummy trench. The dummy polysilicon is spaced apart from the gate polysilicon and may be connected to the emitter electrode.

Abstract: A semiconductor device equipped with a primary semiconductor element and a temperature detecting element for detecting a temperature of the primary semiconductor element. The device includes a first semiconductor layer of a first conductivity type that forms the primary semiconductor element. A second semiconductor region of a second conductivity type is provided in the first semiconductor layer. A third semiconductor region of the first conductivity type is provided in the second semiconductor region. The temperature detecting element is provided in the third semiconductor region and is separated from the first semiconductor layer by a PN junction.

Abstract: A trench-type insulated-gate semiconductor device is disclosed that includes unit cells having a trench gate structure that are scattered uniformly throughout the active region of the device. The impurity concentration in the portion of a p-type base region, sandwiched between an n+-type emitter region and an n-type drift layer and in contact with a gate electrode formed in the trench via a gate insulator film, is the lowest in the portion thereof sandwiched between the bottom plane of n+-type emitter regions and the bottom plane of p-type base region and parallel to the major surface of a silicon substrate. The trench-type insulate-gate semiconductor device according to the invention minimizes the variation of the gate threshold voltage.

Abstract: A semiconductor device equipped with a primary semiconductor element and a temperature detecting element for detecting a temperature of the primary semiconductor element. The device includes a first semiconductor layer of a first conductivity type that forms the primary semiconductor element. A second semiconductor region of a second conductivity type is provided in the first semiconductor layer. A third semiconductor region of the first conductivity type is provided in the second semiconductor region. The temperature detecting element is provided in the third semiconductor region and is separated from the first semiconductor layer by a PN junction.

Abstract: A trench-type insulated-gate semiconductor device is disclosed that includes unit cells having a trench gate structure that are scattered uniformly throughout the active region of the device. The impurity concentration in the portion of a p-type base region, sandwiched between an n+-type emitter region and an n-type drift layer and in contact with a gate electrode formed in the trench via a gate insulator film, is the lowest in the portion thereof sandwiched between the bottom plane of n+-type emitter regions and the bottom plane of p-type base region and parallel to the major surface of a silicon substrate. The trench-type insulate-gate semiconductor device according to the invention minimizes the variation of the gate threshold voltage.

Abstract: A gate driving device includes an IGBT and a gate drive circuit, which includes a gate resistor and a gate drive unit. The gate of the IGBT is connected to the gate resistor, and the emitter of the IGBT is connected to a low voltage potential. The peak impurity concentration of the collector of the IGBT is equal to or greater than 1×1016 cm?3, and the time constant, which is the product of a gate input capacitance (Cg) of the IGBT and a resistance value of the gate resistor (Rg) is equal to or less than 500 ns. The IGBT is turned ON or OFF by inputting an ON or OFF signal respectively to the gate via the gate resistor. The gate driving device can lower the spike voltage and reduce the turn-off power loss at the same time in an inductive load circuit when the IGBT is turned off.

Abstract: A trench-type IGBT includes a silicon substrate, a lightly doped n-type drift layer on the silicon substrate, and a p-type base layer on the n-type drift layer. The p-type base layer is doped more heavily than the n-type drift layer, and is formed of first regions and second regions. N+-type source regions are formed selectively in the surface portions of the first regions of p-type base layer. Trenches are dug from the surfaces of n+-type source regions down to the n-type drift layer through the p-type base layer. A gate oxide film covers the inner surface of each trench. Gate electrodes are provided in the trenches, wherein the gate electrodes face the p-type base layer via respective gate oxide films. An emitter electrode is in direct contact with the first regions of p-type base layer and n+-type source regions. A collector electrode is provided on the back surface of silicon substrate.

Abstract: A trench-type IGBT includes a silicon substrate, a lightly doped n-type drift layer on the silicon substrate, and a p-type base layer on the n-type drift layer. The p-type base layer is doped more heavily than the n-type drift layer, and is formed of first regions and second regions. N+-type source regions are formed selectively in the surface portions of the first regions of p-type base layer. Trenches are dug from the surfaces of n+-type source regions down to the n-type drift layer through the p-type base layer. A gate oxide film covers the inner surface of each trench. A gate electrodes are provided in the trenches, wherein the gate electrodes face the p-type base layer via respective gate oxide films. An emitter electrode is in direct contact with the first regions of p-type base layer and n+-type source regions. A collector electrode is provided on the back surface of silicon substrate.