Patents by Inventor Yuichi Oshino
Yuichi Oshino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9653557Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region having a second conductivity type, a first insulating layer on the first and second semiconductor regions, and field plate electrodes are provided in the first insulating layer at different distances from the first semiconductor layer. A first field plate electrode is at a first distance, a second field plate electrode is at a second distance greater than the first distance, and a third field plate electrode is at a distance greater than the second distance. The first through third field plate electrodes are electrically connected to each other and the third electrode is electrically connected to the second semiconductor region.Type: GrantFiled: March 3, 2014Date of Patent: May 16, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tomoko Matsudai, Yuichi Oshino, Keiko Kawamura, Bungo Tanaka
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Patent number: 9620631Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a pair of conductive bodies, a third semiconductor layer of the second conductivity type, and a fourth semiconductor layer of the first conductivity type. The second semiconductor layer is provided on the first semiconductor layer on the first surface side. The pair of conductive bodies are provided via an insulating film in a pair of first trenches extending across the second semiconductor layer from a surface of the second semiconductor layer to the first semiconductor layer. The third semiconductor layer is selectively formed on the surface of the second semiconductor layer between the pair of conductive bodies and has a higher second conductivity type impurity concentration in a surface of the third semiconductor layer than the second semiconductor layer.Type: GrantFiled: March 18, 2013Date of Patent: April 11, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tomoko Matsudai, Tsuneo Ogura, Yuichi Oshino, Hideaki Ninomiya, Kazutoshi Nakamura
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Patent number: 9337189Abstract: According to one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode; a second semiconductor layer provided between the first semiconductor layer and the second electrode, and the second semiconductor layer having a lower impurity concentration than the first semiconductor layer; a first semiconductor region provided between part of the second semiconductor layer and the second electrode; a second semiconductor region provided between a portion different from the part of the second semiconductor layer and the second electrode, and the second semiconductor region being in contact with the first semiconductor region; and a third semiconductor region provided between at least part of the first semiconductor region and the second electrode.Type: GrantFiled: May 11, 2015Date of Patent: May 10, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Tomoko Matsudai, Yuichi Oshino, Shinichiro Misu, Yoshiko Ikeda, Kazutoshi Nakamura
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Patent number: 9214535Abstract: A collector layer of a first conductivity type is provided in the IGBT region and the boundary region and functions as a collector of the IGBT in the IGBT region. A cathode layer of a second conductivity type is provided in the diode region apart from the collector layer and functions as a cathode of the diode. A drift layer of the second conductivity type is provided in the IGBT region, the boundary region, and the diode region, the drift layer being provided on sides of the collector layer and the cathode layer opposite the first electrode. A diffusion layer of the first conductivity type is provided in the boundary region on a side of the drift layer opposite the first electrode.Type: GrantFiled: September 10, 2013Date of Patent: December 15, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Tomoko Matsudai, Tsuneo Ogura, Kazutoshi Nakamura, Yuichi Oshino, Hideaki Ninomiya, Yoshiko Ikeda
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Publication number: 20150243656Abstract: According to one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode; a second semiconductor layer provided between the first semiconductor layer and the second electrode, and the second semiconductor layer having a lower impurity concentration than the first semiconductor layer; a first semiconductor region provided between part of the second semiconductor layer and the second electrode; a second semiconductor region provided between a portion different from the part of the second semiconductor layer and the second electrode, and the second semiconductor region being in contact with the first semiconductor region; and a third semiconductor region provided between at least part of the first semiconductor region and the second electrode.Type: ApplicationFiled: May 11, 2015Publication date: August 27, 2015Inventors: Tsuneo Ogura, Tomoko Matsudai, Yuichi Oshino, Shinichiro Misu, Yoshiko Ikeda, Kazutoshi Nakamura
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Patent number: 9059236Abstract: According to one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode; a second semiconductor layer provided between the first semiconductor layer and the second electrode, and the second semiconductor layer having a lower impurity concentration than the first semiconductor layer; a first semiconductor region provided between part of the second semiconductor layer and the second electrode; a second semiconductor region provided between a portion different from the part of the second semiconductor layer and the second electrode, and the second semiconductor region being in contact with the first semiconductor region; and a third semiconductor region provided between at least part of the first semiconductor region and the second electrode.Type: GrantFiled: August 29, 2013Date of Patent: June 16, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Tomoko Matsudai, Yuichi Oshino, Shinichiro Misu, Yoshiko Ikeda, Kazutoshi Nakamura
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Publication number: 20140374791Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region having a second conductivity type, a first insulating layer on the first and second semiconductor regions, and field plate electrodes are provided in the first insulating layer at different distances from the first semiconductor layer. A first field plate electrode is at a first distance, a second field plate electrode is at a second distance greater than the first distance, and a third field plate electrode is at a distance greater than the second distance. The first through third field plate electrodes are electrically connected to each other and the third electrode is electrically connected to the second semiconductor region.Type: ApplicationFiled: March 3, 2014Publication date: December 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomoko MATSUDAI, Yuichi OSHINO, Keiko KAWAMURA, Bungo TANAKA
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Patent number: 8853775Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having first and second main surfaces, control electrodes disposed in trenches on the first main surface of the semiconductor substrate and extending in a first direction parallel to the first main surface, and control interconnects disposed on the first main surface of the semiconductor substrate and extending in a second direction perpendicular to the first direction. The semiconductor substrate includes a first semiconductor layer of a first conductivity type, second semiconductor layers of a second conductivity type on a surface of the first semiconductor layer on a first main surface side, third semiconductor layers of the first conductivity type disposed on surfaces of the second semiconductor layers on the first main surface side and extending in the second direction, and a fourth semiconductor layer of the second conductivity type on the second main surface of the semiconductor substrate.Type: GrantFiled: September 9, 2013Date of Patent: October 7, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Kazutoshi Nakamura, Hideaki Ninomiya, Tomoko Matsudai, Yuichi Oshino
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Publication number: 20140124832Abstract: According to one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode; a second semiconductor layer provided between the first semiconductor layer and the second electrode, and the second semiconductor layer having a lower impurity concentration than the first semiconductor layer; a first semiconductor region provided between part of the second semiconductor layer and the second electrode; a second semiconductor region provided between a portion different from the part of the second semiconductor layer and the second electrode, and the second semiconductor region being in contact with the first semiconductor region; and a third semiconductor region provided between at least part of the first semiconductor region and the second electrode.Type: ApplicationFiled: August 29, 2013Publication date: May 8, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsuneo Ogura, Tomoko Matsudai, Yuichi Oshino, Shinichiro Misu, Yoshiko Ikeda, Kazutoshi Nakamura
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Publication number: 20140084337Abstract: A collector layer of a first conductivity type is provided in the IGBT region and the boundary region and functions as a collector of the IGBT in the IGBT region. A cathode layer of a second conductivity type is provided in the diode region apart from the collector layer and functions as a cathode of the diode. A drift layer of the second conductivity type is provided in the IGBT region, the boundary region, and the diode region, the drift layer being provided on sides of the collector layer and the cathode layer opposite the first electrode. A diffusion layer of the first conductivity type is provided in the boundary region on a side of the drift layer opposite the first electrode.Type: ApplicationFiled: September 10, 2013Publication date: March 27, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomoko Matsudai, Tsuneo Ogura, Kazutoshi Nakamura, Yuichi Oshino, Hideaki Ninomiya, Yoshiko Ikeda
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Publication number: 20140077261Abstract: An upper part of the termination region of the semiconductor substrate, an upper surface of the first diffusion layers and an upper surface of the first oxide film is etched in such a manner that the level of the upper surface of the semiconductor substrate in the termination region including the first oxide film and the first diffusion layers is lower than the level of the upper surface of the semiconductor substrate in the cell region. Then, a second oxide film is formed on the semiconductor substrate. An electrode is formed on the second oxide film so as to extend from the first region toward the cell region to the first diffusion layers in such a manner that the level of an upper surface of the electrode is lower than the level of the upper surface of the semiconductor substrate in the cell region.Type: ApplicationFiled: September 6, 2013Publication date: March 20, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yuichi Oshino, Tomoko Matsudai, Kazutoshi Nakamura, Shinichiro Misu, Takuma Hara
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Publication number: 20140077258Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having first and second main surfaces, control electrodes disposed in trenches on the first main surface of the semiconductor substrate and extending in a first direction parallel to the first main surface, and control interconnects disposed on the first main surface of the semiconductor substrate and extending in a second direction perpendicular to the first direction. The semiconductor substrate includes a first semiconductor layer of a first conductivity type, second semiconductor layers of a second conductivity type on a surface of the first semiconductor layer on a first main surface side, third semiconductor layers of the first conductivity type disposed on surfaces of the second semiconductor layers on the first main surface side and extending in the second direction, and a fourth semiconductor layer of the second conductivity type on the second main surface of the semiconductor substrate.Type: ApplicationFiled: September 9, 2013Publication date: March 20, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Kazutoshi Nakamura, Hideaki Ninomiya, Tomoko Matsudai, Yuichi Oshino
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Publication number: 20140070266Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a pair of conductive bodies, a third semiconductor layer of the second conductivity type, and a fourth semiconductor layer of the first conductivity type. The second semiconductor layer is provided on the first semiconductor layer on the first surface side. The pair of conductive bodies are provided via an insulating film in a pair of first trenches extending across the second semiconductor layer from a surface of the second semiconductor layer to the first semiconductor layer. The third semiconductor layer is selectively formed on the surface of the second semiconductor layer between the pair of conductive bodies and has a higher second conductivity type impurity concentration in a surface of the third semiconductor layer than the second semiconductor layer.Type: ApplicationFiled: March 18, 2013Publication date: March 13, 2014Inventors: Tomoko MATSUDAI, Tsuneo OGURA, Yuichi OSHINO, Hideaki NINOMIYA, Kazutoshi NAKAMURA
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Patent number: 8664692Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first conductivity type cathode layer, a first conductivity type base layer, a second conductivity type anode layer, a second conductivity type semiconductor layer, a first conductivity type semiconductor layer, an buried body, and a second electrode. The first conductivity type semiconductor layer is contiguous to the second conductivity type semiconductor layer in a first direction, and extends on a surface of the anode layer in a second direction that intersects perpendicularly to the first direction. The buried body includes a bottom portion and a sidewall portion. The bottom portion is in contact with the base layer. The sidewall portion is in contact with the base layer, the anode layer, the second conductivity type semiconductor layer and the first conductivity type semiconductor layer. The buried body extends in the first direction.Type: GrantFiled: August 30, 2012Date of Patent: March 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Tomoko Matsudai, Yuichi Oshino
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Publication number: 20130248882Abstract: In a semiconductor device, transistor cells and diode cells are formed on a single semiconductor substrate of a first conductivity type. A first semiconductor layer of a second conductivity type is formed in a transistor cell region and at a lower side of the substrate. A second semiconductor layer of the first conductivity type is formed in a region adjacent to the transistor cell region and at the lower side of the substrate. Gate electrodes are formed at an upper side of the substrate. A third semiconductor layer of the second conductivity type and a fourth semiconductor layer of the first conductivity type are formed between the gate electrodes. A fifth semiconductor layer of the first conductivity type is formed above the first semiconductor layer in the transistor cell region. A first and a second electrode are formed on both sides of the substrate.Type: ApplicationFiled: March 4, 2013Publication date: September 26, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsuneo OGURA, Tomoko MATSUDAI, Yuichi OSHINO, Hideaki NINOMIYA
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Publication number: 20130221401Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first conductivity type cathode layer, a first conductivity type base layer, a second conductivity type anode layer, a second conductivity type semiconductor layer, a first conductivity type semiconductor layer, an buried body, and a second electrode. The first conductivity type semiconductor layer is contiguous to the second conductivity type semiconductor layer in a first direction, and extends on a surface of the anode layer in a second direction that intersects perpendicularly to the first direction. The buried body includes a bottom portion and a sidewall portion. The bottom portion is in contact with the base layer. The sidewall portion is in contact with the base layer, the anode layer, the second conductivity type semiconductor layer and the first conductivity type semiconductor layer. The buried body extends in the first direction.Type: ApplicationFiled: August 30, 2012Publication date: August 29, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Tsuneo OGURA, Tomoko MATSUDAI, Yuichi OSHINO
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Patent number: 5952682Abstract: A semiconductor device has a low lifetime layer in a selective portion of an N-type drain region to prevent a change in the element characteristic due to Fe contaminants, even if the device is kept at a high temperature. An impurity of a concentration of at least 10.sup.16 atoms/cm.sup.3 is deposited on a first main surface of the N-type drain region, and diffused into the region to a depth of 10 .mu.m, thereby forming a P-type anode region. An anode metal electrode is formed on the surface of the anode region. A P-type base region and an N-type source region are formed in a second main surface of the N-type drain region by ion injection or the like. A gate electrode is formed above the second main surface with a gate oxide film interposed therebetween. A metal gate electrode is formed in contact with the gate electrode. A source metal electrode is formed on the source region and the base region so as to short-circuit them. The low lifetime layer is formed in a selective portion of the N-type drain region.Type: GrantFiled: December 16, 1996Date of Patent: September 14, 1999Assignee: Kabushiki Kaisha ToshibaInventor: Yuichi Oshino