Patents by Inventor Yuichi Saito

Yuichi Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130068578
    Abstract: A cask cushioning body includes an end-surface side member (2) in which a plurality of plates (21, 22) made of steel are formed at a distance between plate surfaces of the plates (21, 22) that face each other, and in which the plate surfaces of the plates (21, 22) are arranged along an end surface (100a) of a cask (100), and a circumferential-surface side member (3) that forms a cylindrical body (31) made of steel, one end of which is connected to a periphery of the end-surface side member (2), and that is arranged along an end-portion outer-circumferential surface (100b), wherein an impact absorber (4) that absorbs an impact by deforming is provided outside of the end-surface side member (2) and the circumferential-surface side member (3).
    Type: Application
    Filed: June 28, 2011
    Publication date: March 21, 2013
    Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Yuichi Saito, Junichi Kishimoto, Tadashi Kimura, Akio Kitada, Hiroki Tamaki
  • Patent number: 8398116
    Abstract: An airbag for a vehicle, the airbag formed as a bag body by sewing together a base cloth, wherein the bag body is configured so that a direction in which the bag body unfolds expands from a base end side of the bag body to a tip end side, and, the bag body includes a tensional force providing mechanism generating a tensional force pulling an upper rim of the bag body toward an outer side by forming a tension line extending so as to cross with the direction in which the bag body unfolds, along a side surface of the bag body.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: March 19, 2013
    Assignee: Honda Motor Co., Ltd.
    Inventors: Kazuhiro Onda, Nobuhiro Kawamoto, Itaru Genpei, Makoto Uchikawa, Takashi Kikuchi, Yukio Hiruta, Yuichi Saito
  • Publication number: 20130061409
    Abstract: An erasing device of one embodiment includes a conveyance unit that conveys a sheet; a pair of rotating brushes is provided corresponding to both side portions in a width direction perpendicular to a sheet conveyance direction of the sheet conveyed by the conveyance unit, the rotating brushes being provided to oppose to each other, nipping the conveyed sheet, the rotating brushes rotating in the same direction as the sheet conveyance direction such that a circumferential speed of the brush tip has a higher speed than a conveyance speed of the sheet, the rotating brushes rolling and correcting a corner fold portion which occurs on the sheet conveyed by the brush tip portion while rotating; and an erasing unit is provided downstream in the sheet conveyance direction than the rotating brush, the erasing unit erasing an image which is formed on the sheet.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 14, 2013
    Applicants: Toshiba Tec Kabushiki Kaisha, Kabushiki Kaisha Toshiba
    Inventors: Yoichi Yamaguchi, Ken Iguchi, Isao Yahata, Takahiro Kawaguchi, Yoshiaki Sugizaki, Kikuo Mizutani, Hiroyuki Taki, Hiroyuki Tsuchihashi, Chiaki Iizuka, Hidetoshi Yokochi, Toshiaki Oshiro, Hiroyuki Hazu, Hiroyuki Sugiyama, Yuichi Saito, Jun Ishii
  • Patent number: 8378348
    Abstract: A semiconductor device 101 includes: a substrate 1; an active layer 4 provided on the substrate 1 and including a channel region 4c, and a first region 4a and a second region 4b that are respectively located on opposite sides of the channel region 4c; first and second contact layers 6a and 6b respectively in contact with the first and second regions 4a and 4b of the active layer 4; a first electrode 7 electrically coupled to the first region 4a via the first contact layer 6a; a second electrode 8 electrically coupled to the second region 4b via the second contact layer 6b; and a gate electrode 2 provided such that a gate insulating layer 3 is interposed between the gate electrode 2 and the active layer 4, the gate electrode 2 being configured to control a conductivity of the channel region 4c. The active layer 4 contains silicon. The semiconductor device further includes an oxygen-containing silicon layer 5 between the active layer 4 and the first and second contact layers 6a, 6b.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: February 19, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yuichi Saito, Masao Moriguchi, Akihiko Kohno
  • Publication number: 20130002784
    Abstract: According to an embodiment, a method for color erasing process includes the steps of : supplying a power to a heat source configured to heat a sheet having an image formed thereon using a color erasable material so as to cause heat generation as warming-up control; stopping the power supply to the heat source for a predetermined period of time in the warming-up control if the temperature of the heat source is increased starting from a temperature lower than a predetermined reference value that is lower than a color erasing temperature of the color erasable material and exceeds the predetermined reference value; performing maintenance control that is power supply control to maintain the temperature of the heat source at the target temperature; and performing, after the passage of the predetermined period of time, a color erasing process by the heat source.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 3, 2013
    Applicants: Toshiba Tec Kabushiki Kaisha, Kabushiki Kaisha Toshiba
    Inventors: Ken Iguchi, Isao Yahata, Takahiro Kawaguchi, Yoshiaki Sugizaki, Kikuo Mizutani, Hiroyuki Taki, Hiroyuki Tsuchihashi, Chiaki Iizuka, Hidetoshi Yokochi, Toshiaki Oshiro, Hiroyuki Hazu, Yoichi Yamaguchi, Hiroyuki Sugiyama, Yuichi Saito
  • Publication number: 20130002783
    Abstract: According to one embodiment, an erasing apparatus includes a paper feeding unit configured to feed a sheet having an image recorded, an erasing unit including a pressing roller and a heater that has a shape following the outer circumference of the pressing roller and includes a contact area with the pressing roller, the erasing unit being configured to erase the image formed on the sheet fed to a contact section of the pressing roller and the heater from the paper feeding unit, a temperature detecting unit configured to detect the temperature of the heater, a controller configured to control the heater according to the temperature detected by the temperature detecting unit, and a paper discharge unit configured to discharge the sheet on which the image is erased by the erasing unit.
    Type: Application
    Filed: June 20, 2012
    Publication date: January 3, 2013
    Applicants: Toshiba Tec Kabushiki Kaisha, Kabushiki Kaisha Toshiba
    Inventors: Kikuo MIZUTANI, Isao YAHATA, Takahiro KAWAGUCHI, Yoshiaki SUGIZAKI, Ken IGUCHI, Hiroyuki TAKI, Hiroyuki TSUCHIHASHI, Chiaki IIZUKA, Hidetoshi YOKOCHI, Toshiaki OSHIRO, Hiroyuki HAZU, Yoichi YAMAGUCHI, Hiroyuki SUGIYAMA, Yuichi SAITO, Jun ISHII
  • Publication number: 20130001050
    Abstract: A sheet processing apparatus includes: a conveying member configured to convey a sheet; a first opening section including a conveyance guide section arranged on the opposite side of the conveying member across a conveying path and configured to form the conveying path and a first pivot shaft configured to pivotably support the conveyance guide section, the first opening section being configured to form the conveying path using the conveyance guide section if changing to a closed state and open the conveying path if changing to an open state; and a second opening section including a cover section configured to cover the first opening section if the first opening section changes to the closed state and a second pivot shaft configured to pivotably support the cover section, the second opening section being configured to cause, if pivoting, the first opening section to pivot following the second opening section.
    Type: Application
    Filed: June 21, 2012
    Publication date: January 3, 2013
    Applicants: Toshiba Tec Kabushiki Kaisha, Kabushiki Kaisha Toshiba
    Inventors: Toshiaki OSHIRO, Isao Yahata, Takahiro Kawaguchi, Yoshiaki Sugizaka, Kikuo Mizutani, Hiroyuki Taki, Hiroyuki Tsuchihashi, Chiaki IIzuka, Hidetoshi Yokochi, Ken Iguchi, Hiroyuki Hazu, Yoichi Yamaguchi, Hiroyuki Sugiyama, Yuichi Saito
  • Publication number: 20130003138
    Abstract: A shading device includes: a shading member to pass a conveying path for conveying a recoding medium to plural image reading sections and reach the plural image reading sections; and a moving member to move the shading member between the plural image reading sections and a retracted position on the outside of the conveying path.
    Type: Application
    Filed: May 30, 2012
    Publication date: January 3, 2013
    Applicants: Toshiba Tec Kabushiki Kaisha, Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Sugizaki, Hidetoshi Yokochi, Hiroyuki Tsuchihashi, Isao Yahata, Takahiro Kawaguchi, Ken Iguchi, Kikuo Mizutani, Hiroyuki Taki, Chiaki Ilzuka, Toshiaki Oshiro, Hiroyuki Hazu, Yoichi Yamaguchi, Hiroyuki Sugiyama, Yuichi Saito, Jun Ishii
  • Publication number: 20130003134
    Abstract: A sheet loading apparatus includes a loading member which loads the sheet discharged by the discharge member, a tip support member which abuts against the leading edge of the sheet discharged by the discharge member in the sheet discharge direction, a rotation member which abuts against an upper surface of the sheet discharged to the loading member, and is rotated to transport the sheet to the stopper side, and a control section which controls a transport amount of the sheet through the rotation member based on a loading amount of the sheet loaded on the loading member.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 3, 2013
    Applicants: Toshiba Tec Kabushiki Kaisha, Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki HAZU, Ken IGUCHI, Yuichi SAITO, Isao YAHATA, Takahiro KAWAGUCHI, Yoshiaki SUGIZAKI, Kikuo MIZUTANI, Hiroyuki TAKI, Hiroyuki TSUCHIHASHI, Chiaki IIZUKA, Hidetoshi YOKOCHI, Toshiaki OSHIRO, Yoichi YAMAGUCHI, Hiroyuki SUGIYAMA, Jun ISHII
  • Publication number: 20120319348
    Abstract: A sheet feed apparatus which includes a sheet feed tray in which a plurality of sheets is loaded in piles; a sheet feed roller which is provided at a forward position of the sheet feed tray in a sheet feed direction, and sends the loaded sheets inside thereof; and a lift detection sensor which detects, by using a movable lever, a lift of a sheet bundle which occurs when the sheet bundle, of which a rear or a side in a sheet feed direction is bound, is sent by the sheet feed roller therein, the lift detection sensor being provided at a side position of the sheet bundle in a width direction and at a backward position with respect to the center of the sheet bundle in the sheet feed direction.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 20, 2012
    Applicants: Toshiba Tec Kabushiki Kaisha, Kabushiki Kaisha Toshiba
    Inventors: Toshiaki OSHIRO, Ken Iguchi, Isao Yahata, Kikuo Mizutani, Hiroyuki Taki, Chiaki Iizuka, Hidetoshi Yokochi, Yoshiaki Sugizaki, Takahiro Kawaguchi, Hiroyuki Tsuchihashi, Hiroyuki Hazu, Yoichi Yamaguchi, Hiroyuki Sugiyama, Yuichi Saito, Jun Ishii
  • Publication number: 20120306984
    Abstract: According to an embodiment, a sheet discharging device includes: a first conveying path configured to guide a sheet to be conveyed; a second conveying path branched from the first conveying path at a branch point of the first conveying path; a sorting section configured to sort a sheet being conveyed on the first conveying path into either a downstream side of the branch point on the first conveying path or the second conveying path; a first discharge tray configured to receive a sheet discharged from the first conveying path at a first sheet loading surface; and a second discharge tray placed below the first discharge tray and configured to receive a sheet discharged from the second conveying path at a second sheet loading surface whose distance to the first sheet loading surface increases toward a downstream side thereof in a sheet discharging direction.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 6, 2012
    Applicants: TOSHIBA TEC KABUSHIKI KAISHA, KABUSHIKI KAISHA TOSHIBA
    Inventors: Isao YAHATA, Kikuo Mizutani, Takahiro Kawaguchi, Yoshiaki Sugizaki, Ken Iguchi, Hiroyuki Taki, Hiroyuki Tsuchihashi, Chiaki Iizuka, Hidetoshi Yokochi, Toshiaki Oshiro, Hiroyuki Hazu, Yoichi Yamaguchi, Hiroyuki Sugiyama, Yuichi Saito
  • Publication number: 20120306982
    Abstract: According to one embodiment, a color erasing apparatus includes a color erasing section which erases a color of an image formed with an erasable color material on a sheet conveyed at first speed, a reading section which reads an image on the surface of the sheet conveyed at second speed higher than the first speed, a first conveying section, and a second conveying section. The first conveying section includes a first conveying roller arranged downstream in a sheet conveying direction of the color erasing section and conveys the sheet at the first speed. The second conveying section includes a second conveying roller arranged upstream in the sheet conveying direction of the reading section and in a position where the second conveying roller nips the conveyed sheet simultaneously with the first conveying roller. The second conveying section conveys the sheet to the reading section at the second speed.
    Type: Application
    Filed: February 20, 2012
    Publication date: December 6, 2012
    Applicants: Toshiba Tec Kabushiki Kaisha, Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki TAKI, Hiroyuki Tsuchihashi, Takahiro Kawaguchi, Isao Yahata, Yoshiaki Sugizaki, Kikuo Mizutani, Ken Iguchi, Chiaki Ilzuka, Hidetoshi Yokochi, Toshiaki Oshiro, Hiroyuki Hazu, Yoichi Yamaguchi, Hiroyuki Sugiyama, Yuichi Saito
  • Publication number: 20120307314
    Abstract: According to an embodiment, a first discharging unit and a second discharging unit discharge a sheet. A first conveying path extends from a scanning unit to the first discharging unit. A second conveying path branches off from the first conveying path at a branch point of the first conveying path and extends to the second discharging unit. A conveying member discharges the sheet to the first discharging unit when a discharging destination of the sheet is the first discharging unit, and the conveying member makes part of the sheet project from the first conveying path to the first discharging unit, locates an upstream tip end of the sheet in a sheet conveying direction, at a position downstream in the sheet conveying direction from the branch point, and conveys the sheet to switchback to the second conveying path, when the discharging destination of the sheet is the second discharging unit.
    Type: Application
    Filed: May 30, 2012
    Publication date: December 6, 2012
    Applicants: Toshiba Tec Kabushiki Kaisha, Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki SUGIZAKI, Hiroyuki TAKI, Hidetoshi YOKOCHI, Isao YAHATA, Takahiro KAWAGUCHI, Ken IGUCHI, Kikuo MIZUTANI, Hiroyuki TSUCHIHASHI, Chiaki IIZUKA, Toshiaki OSHIRO, Hiroyuki HAZU, Yoichi YAMAGUCHI, Hiroyuki SUGIYAMA, Yuichi SAITO
  • Patent number: 8304297
    Abstract: An active matrix substrate includes base substrate, gate lines, data lines, thin-film transistors and pixel electrodes. The gate lines are formed on the base substrate. The data lines are formed over the gate lines. Each of the data lines crosses all of the gate lines with an insulating film interposed therebetween. The thin-film transistors are formed over the base substrate. Each of the thin-film transistors is associated with one of the gate lines and operates responsive to a signal on the associated gate line. Each of the pixel electrodes is associated with one of the data lines and one of the thin-film transistors and is electrically connectable to the associated data line by way of the associated thin-film transistor. Each of the pixel electrodes and the associated thin-film transistor are connected together by way of a conductive member.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: November 6, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Okada, Yuichi Saito, Shinya Yamakawa, Atsushi Ban, Masaya Okamoto, Hiroyuki Ohgami
  • Patent number: 8283218
    Abstract: A production method of a semiconductor element having a channel includes forming a resist pattern film on a thin film formed on a substrate, and pattering the thin film by etching. The production method also includes forming a second resist pattern film by applying a fluid resist material inside a channel groove after channel etching or inside a resist groove formed above a channel region before channel etching. The production method may also include forming a gate electrode, a gate insulating film, a semiconductor film, and a conductive film on an insulating substrate. The method may include applying the fluid resist material inside the channel groove, thereby forming the second resist pattern film, and patterning the semiconductor film using at least the second resist pattern film.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: October 9, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yuichi Saito, Takeshi Hara
  • Publication number: 20120148327
    Abstract: According to one embodiment, a erasing apparatus includes: a paper feeding section configured to feed a recording medium on which a erasable image is recorded to a conveying path; a conveying section configured to convey the recording medium along the conveying path; a erasing section configured to erase a color of the image on the recording medium; a sensor configured to detect the recording medium conveyed through the erasing section by the conveying section; and a control section configured to perform, if the sensor detects occurrence of a jam of the recording medium, control to convey the recording medium present in the conveying path.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 14, 2012
    Applicants: Toshiba Tec Kabushiki Kaisha, Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Taki, Ken Iguchi, Isao Yahata, Takahiro Kawaguchi, Hiroyuki Taguchi, Hiroyuki Tsuchihashi, Yoshiaki Sugizaki, Kikuo Mizutani, Chiaki Iizuka, Hidetoshi Yokochi, Toshiaki Oshiro, Hiroyuki Hazu, Yoici Yamaguchi, Hiroyuki Sugiyama, Yuichi Saito, Jun Ishii
  • Patent number: 8174013
    Abstract: A semiconductor device includes a semiconductor layer having a channel region, an impurity layer having a source region and a drain region, and a gate electrode provided so as to face the semiconductor layer with a gate insulating film interposed therebetween. The semiconductor layer has a layered structure of at least a first amorphous film and a crystalline film including a crystal phase, and the first amorphous film is formed directly on the gate insulating film.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: May 8, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masao Moriguchi, Yuichi Saito
  • Publication number: 20120049193
    Abstract: A semiconductor device 100 according to the present invention includes a TFT 120 and a TFT 140. The TFT 120 has a gate electrode 122, a semiconductor layer 130 including a microcrystalline semiconductor film 132, and a gate insulating layer 124 provided between the gate electrode 122 and the semiconductor layer 130. The TFT 140 has a gate electrode 142, a semiconductor layer 150 including a microcrystalline semiconductor film 152, and a gate insulating layer 144 provided between the gate electrode 142 and the semiconductor layer 150. The thickness and layer structure of the semiconductor layer 150 of the TFT 140 are different from those of the semiconductor layer 130 of the TFT 120.
    Type: Application
    Filed: February 2, 2010
    Publication date: March 1, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yuichi Saito, Masao Moriguchi, Atsuyuki Hoshino, Tokuo Yoshida
  • Publication number: 20120043543
    Abstract: Disclosed is a semiconductor device provided with the following: an active layer 6 formed on a substrate 1 having a channel region 6c, a first region 6a located on one side of the channel region 6c, and a second region 6b located on the other side of the channel region 6c; a contact formation layer 8 that is formed on the active layer 6 and that has a separation region 9, a first contact region 8a, and a second contact region 8b, the latter two of which are located on the first region 6a and the second region 6b of the active layer, respectively; a first electrode 10 electrically connected to the first region 6a through the first contact region 8a; a second electrode 11 electrically connected to the second region 6b through the second contact region 8b; and a gate electrode 2 provided with respect to the active layer 6 through a gate insulating layer 4.
    Type: Application
    Filed: April 15, 2010
    Publication date: February 23, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yuichi Saito, Masao Moriguchi
  • Publication number: 20110169005
    Abstract: A diode 201 includes a gate electrode 2, a gate insulating layer 5 provided on the gate electrode 2, at least one semiconductor layer 6, 7 provided on the gate insulating layer 5 and which includes a first region 6a and a second region 7b, a first electrode 10 which is provided on the first region 6a and which is electrically coupled to the first region 6a and the gate electrode 2, and a second electrode 12 which is provided on the second region 7b and which is electrically coupled to the second region 7b. The at least one semiconductor layer 6, 7 includes a channel region 6c which extends above the gate electrode 2 with the intervention of the gate insulating layer 5 therebetween, and a resistor region 7d which does not extend above the gate electrode 2. When the diode 201 is in an ON state, an electric current path is formed between the first electrode 10 and the second electrode 12, the electric current path including the channel region 6c and the resistor region 7d.
    Type: Application
    Filed: September 1, 2009
    Publication date: July 14, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yuichi Saito, Masao Moriguchi, Tokuo Yoshida, Yasuaki Iwase, Yohsuke Kanzaki, Mayuko Sakamoto