Patents by Inventor Yuichi Sano
Yuichi Sano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20200051957Abstract: A semiconductor device includes a substrate, a first semiconductor chip on the substrate, a first adhesive material on the first semiconductor chip, a spacer chip on the first adhesive material, a second adhesive material on the spacer chip, a second semiconductor chip on the second adhesive material, and a resin material that covers the first and second semiconductor chips and the spacer chip. The spacer chip has a first region with which the resin material comes in contact is roughened and a second region that is different from the first region.Type: ApplicationFiled: February 26, 2019Publication date: February 13, 2020Inventor: Yuichi SANO
-
Publication number: 20190363042Abstract: A semiconductor device includes a semiconductor chip mounted to a mounting substrate with an interposer interposed therebetween such that a surface of the semiconductor chip on which bumps are formed faces a surface of the mounting substrate. The mounting substrate has a plurality of metal parts formed as terminals on a surface of the mounting substrate and in contact with electrode pads connected to multilayer wiring. The semiconductor chip has a plurality of functional elements formed in an inner layer and a plurality of bumps formed in contact with element wiring lines of the functional elements such that the bumps protrude from the surface of the semiconductor chip. The interposer has a plurality of first recesses formed in the surface of the interposer facing the surface of the semiconductor chip on which the bumps are formed such that the first recesses accommodate only the bumps.Type: ApplicationFiled: May 14, 2019Publication date: November 28, 2019Inventors: Yuichi SANO, Atsushi KUROKAWA
-
Publication number: 20190287919Abstract: According to one embodiment, a semiconductor device includes a substrate including a substrate receiving surface, a side surface, and at least two ground wirings embedded therein and extending to, and exposed at, the side surface, a semiconductor chip mounted on the receiving surface of the substrate, a sealing resin layer over the substrate and the semiconductor chip, the sealing resin layer having an outer surface comprising an upper surface and a side surface, and a conductive shield layer located on the upper surface of the sealing resin layer, the side surface of the sealing resin layer, and the side surface of the substrate, and connected to the at least two ground wirings exposed at the side surface of the substrate, wherein the at least two ground wirings are separated from each other within the substrate, and connected to each other along the side surface of the substrate.Type: ApplicationFiled: September 3, 2018Publication date: September 19, 2019Inventor: Yuichi SANO
-
Publication number: 20190267479Abstract: A semiconductor device includes a semiconductor element including a bipolar transistor disposed on a compound semiconductor substrate, a collector electrode, a base electrode, and an emitter electrode, the bipolar transistor including a collector layer, a base layer, and an emitter layer, the collector electrode being in contact with the collector layer, the base electrode being in contact with the base layer, the emitter electrode being in contact with the emitter layer; a protective layer disposed on one surface of the semiconductor element; an emitter redistribution layer electrically connected to the emitter electrode via a contact hole in the protective layer; and a stress-relieving layer disposed between the emitter redistribution layer and the emitter layer in a direction perpendicular to a surface of the compound semiconductor substrate.Type: ApplicationFiled: February 6, 2019Publication date: August 29, 2019Inventors: Atsushi KUROKAWA, Yuichi SANO
-
Patent number: 10121746Abstract: A semiconductor device includes a semiconductor substrate, a first metal layer, an insulation layer, an organic layer, and a second metal layer. The first metal layer, the insulation layer, the organic layer, and the second metal layer are sequentially stacked on a surface of the semiconductor substrate. The first metal layer and the second metal layer are electrically connected to each other through vias formed in the insulation layer and the organic layer. The second metal layer includes an electrode pad at a position corresponding to the positions of the vias. At the interface between the surface of the semiconductor substrate and the first metal layer, a patch portion having a trapezoidal cross-sectional shape is disposed directly below the vias.Type: GrantFiled: November 16, 2017Date of Patent: November 6, 2018Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Kazuya Kobayashi, Yuichi Sano, Daisuke Tokuda, Hiroaki Tokuya
-
Publication number: 20180247895Abstract: A semiconductor device includes electrodes which contain Au and which are placed above conductive layers in a region adjacent to stacked insulating films and also includes base layers which are composed of compositionally modulated layers and which are placed between the electrodes and the conductive layers. The base layers include lateral end sections composed of single layers projecting from lateral end sections of the electrodes in the direction of the interlayer interface between the insulating films; sections which are located under the electrodes and of which a major compositional component is Ti or Ti and W; and projecting sections which project from under the electrodes in the direction of the interlayer interface between the insulating films and of which compositional components are compositionally modulated to Ti and O, to Ti, O, and N, or to Ti, W, O, and N.Type: ApplicationFiled: February 23, 2018Publication date: August 30, 2018Inventors: Yuichi SANO, Atsushi KUROKAWA, Kazuya KOBAYASHI
-
Publication number: 20180145028Abstract: A semiconductor device includes a semiconductor substrate, a first metal layer, an insulation layer, an organic layer, and a second metal layer. The first metal layer, the insulation layer, the organic layer, and the second metal layer are sequentially stacked on a surface of the semiconductor substrate. The first metal layer and the second metal layer are electrically connected to each other through vias formed in the insulation layer and the organic layer. The second metal layer includes an electrode pad at a position corresponding to the positions of the vias. At the interface between the surface of the semiconductor substrate and the first metal layer, a patch portion having a trapezoidal cross-sectional shape is disposed directly below the vias.Type: ApplicationFiled: November 16, 2017Publication date: May 24, 2018Inventors: Kazuya Kobayashi, Yuichi Sano, Daisuke Tokuda, Hiroaki Tokuya
-
Patent number: 9099586Abstract: To provide a nitride semiconductor light-emitting element in which a buffer layer provided between an n-type nitride semiconductor layer and a p-type nitride semiconductor layer has a first buffer layer expressed by an equation of Inx1Ga1-x1N (0<x1?1) and a second buffer layer expressed by an equation of Inx2Ga1-x2N (0?x2<1, x2<x1) alternately laminated, an In composition x1 of the first buffer layer is changed, and the In composition x1 of at least one layer of the first buffer layers is higher than an In composition of the active layer, and a method for producing the same.Type: GrantFiled: November 19, 2012Date of Patent: August 4, 2015Assignee: SHARP KABUSHIKI KAISHAInventors: Masaya Ueda, Yoshihiro Ueta, Yuichi Sano, Toshiyuki Okumura
-
Patent number: 8833419Abstract: A rubber-cord complex having an improved wet heat adhesive property between a rubber and a cord comprising a drawn plated wire, and including a metal cord comprising a drawn plated wire prepared by providing a brass plated layer on the surface of an element wire and drawing the resulting plated wire, and a rubber vulcanized and bonded to the cord, wherein in a wet heat deterioration state of the drawn plated wire after being subjected to the vulcanization to bond the rubber thereto and further held under an atmosphere having a temperature of 50 to 100° C. and a humidity of 60 to 100% for one hour to 20 days, the average grain size of crystal grains present in the brass plated layer is not more than 50 nm, and the grain boundary of the crystal grains has a fractal dimension of 1.001 to 1.500.Type: GrantFiled: February 15, 2012Date of Patent: September 16, 2014Assignees: Sumitomo Rubber Industries, Ltd., Nippon Steel & Sumitomo Metal Corporation, Sumitomo (SEI) Steel Wire Corp.Inventors: Shinichi Miyazaki, Junichi Kodama, Yasuo Sakai, Keisuke Aramaki, Yuichi Sano, Kenichi Okamoto
-
Patent number: 8833420Abstract: Rubber-cord complex 9 having improved wet heat adhesive property between rubber and cord. The rubber-cord complex includes cord 10 comprising drawn plated wire 17 prepared by providing brass plated layer 16E on surface of element wire 15 and drawing the resulting plated wire and rubber 12 vulcanized and bonded to cord 10. The rubber-cord complex 9 has adhesion reaction layer 25 (formed by cross-linking sulfur and copper) between rubber 12 and brass plated layer 16E. Adhesion reaction layer 25 has average thickness of 50-1,000 nm. Interface S between adhesion reaction layer 25 and the rubber has a fractal dimension of 1.001-1.300 in a wet heat deterioration state after being subjected to vulcanization to bond rubber 12 thereto and being held at a temperature of 50-100° C. and a humidity of 60-100% for one hour to 20 days.Type: GrantFiled: February 17, 2012Date of Patent: September 16, 2014Assignees: Sumitomo Rubber Industries, Ltd., Nippon Steel & Sumitomo Metal Corporation, Sumitomo (SEI) Steel Wire Corp.Inventors: Shinichi Miyazaki, Junichi Kodama, Yasuo Sakai, Keisuke Aramaki, Yuichi Sano, Kenichi Okamoto
-
Publication number: 20130134388Abstract: To provide a nitride semiconductor light-emitting element in which a buffer layer provided between an n-type nitride semiconductor layer and a p-type nitride semiconductor layer has a first buffer layer expressed by an equation of Inx1Ga1-x1N (0<x1?1) and a second buffer layer expressed by an equation of Inx2Ga1-x2N (0?x2<1, x2<x1) alternately laminated, an In composition x1 of the first buffer layer is changed, and the In composition x1 of at least one layer of the first buffer layers is higher than an In composition of the active layer, and a method for producing the same.Type: ApplicationFiled: November 19, 2012Publication date: May 30, 2013Inventors: Masaya UEDA, Yoshihiro UETA, Yuichi SANO, Toshiyuki OKUMURA
-
Publication number: 20130062758Abstract: In one embodiment, a semiconductor device has a substrate, a first semiconductor chip, an electrode, a first and second connection member, and a first and second sealing member. The electrode is disposed on the first semiconductor chip and contains Al. The first connection member electrically connects the electrode and the substrate and contains Au or Cu. The first sealing member seals the first semiconductor chip and the first connection member. One or more second semiconductor chips are stacked on the first sealing member. The second sealing member seals the first connection member, the one or more second semiconductor chips, and the one or more second connection members. A ratio of a total weight W1 of Cl ions and Br ions in the first sealing member to a weight W0 of resins of the substrate and the first sealing member is 7.5 ppm or lower.Type: ApplicationFiled: March 16, 2012Publication date: March 14, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Takashi IMOTO, Yoriyasu Ando, Akira Tanimoto, Masaji Iwamoto, Yasuo Takemoto, Hideo Taguchi, Naoto Takebe, Koichi Miyashita, Jun Tanaka, Katsuhiro Ishida, Shogo Watanabe, Yuichi Sano
-
Publication number: 20120199259Abstract: Rubber-cord complex 9 having improved wet heat adhesive property between rubber and cord. The rubber-cord complex includes cord 10 comprising drawn plated wire 17 prepared by providing brass plated layer 16E on surface of element wire 15 and drawing the resulting plated wire and rubber 12 vulcanized and bonded to cord 10. The rubber-cord complex 9 has adhesion reaction layer 25 (formed by cross-linking sulfur and copper) between rubber 12 and brass plated layer 16E. Adhesion reaction layer 25 has average thickness of 50-1,000 nm. Interface S between adhesion reaction layer 25 and the rubber has a fractal dimension of 1.001-1.300 in a wet heat deterioration state after being subjected to vulcanization to bond rubber 12 thereto and being held at a temperature of 50-100° C. and a humidity of 60-100% for one hour to 20 days.Type: ApplicationFiled: February 17, 2012Publication date: August 9, 2012Inventors: Shinichi Miyazaki, Junichi Kodama, Yasuo Sakai, Keisuke Aramaki, Yuichi Sano, Kenichi Okamoto
-
Patent number: 8237295Abstract: According to one embodiment, a semiconductor device includes a first semiconductor element, a first electrode, a ball part, a second electrode, and a wire. The first electrode is electrically connected to the first semiconductor element. The ball part is provided on the first electrode. The wire connects the ball part and the second electrode. A thickness of a turned-back portion at an end of the wire on a side opposite to the second electrode is smaller than a diameter of the wire.Type: GrantFiled: March 21, 2011Date of Patent: August 7, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yuichi Sano, Takashi Imoto, Naoto Takebe, Katsuhiro Ishida, Tomomi Honda, Yasushi Kumagai
-
Publication number: 20120145297Abstract: A rubber-cord complex having an improved wet heat adhesive property between a rubber and a cord comprising a drawn plated wire, and including a metal cord comprising a drawn plated wire prepared by providing a brass plated layer on the surface of an element wire and drawing the resulting plated wire, and a rubber vulcanized and bonded to the cord, wherein in a wet heat deterioration state of the drawn plated wire after being subjected to the vulcanization to bond the rubber thereto and further held under an atmosphere having a temperature of 50 to 100° C. and a humidity of 60 to 100% for one hour to 20 days, the average grain size of crystal grains present in the brass plated layer is not more than 50 nm, and the grain boundary of the crystal grains has a fractal dimension of 1.001 to 1.500.Type: ApplicationFiled: February 15, 2012Publication date: June 14, 2012Inventors: Shinichi Miyazaki, Junichi Kodama, Yasuo Sakai, Keisuke Aramaki, Yuichi Sano, Kenichi Okamoto
-
Publication number: 20120138134Abstract: A stack-type photovoltaic element with improved conversion efficiency having an intermediate layer and a method of manufacturing the same are provided. A stack-type photovoltaic element according to the present invention includes a first photovoltaic element portion (a) and a second photovoltaic element portion from a substrate side, as well as at least one intermediate layer between the first photovoltaic element portion and the second photovoltaic element portion. The intermediate layer is formed from a metal oxide film having an oxygen atom concentration/metal atom concentration ratio not lower than 0.956 and not higher than 0.976.Type: ApplicationFiled: August 25, 2010Publication date: June 7, 2012Inventors: Makoto Higashikawa, Takako Shimizu, Shinya Honda, Yasuaki Ishikawa, Yuichi Sano
-
Publication number: 20120125406Abstract: Disclosed is a stacked photovoltaic element, including: a first photovoltaic element portion including at least one photovoltaic element, stacked over a substrate; an intermediate layer made of a metal oxide, stacked over the first photovoltaic element portion; a buffer layer in an amorphous state, stacked over the intermediate layer; and a second photovoltaic element portion including at least one photovoltaic element, stacked over the buffer layer, wherein a conductive layer of the second photovoltaic element portion in contact with the buffer layer is a microcrystalline layer.Type: ApplicationFiled: August 4, 2010Publication date: May 24, 2012Applicant: Sharp Kabushiki KaishaInventors: Makoto Higashikawa, Takako Shimizu, Shinya Honda, Yasuaki Ishikawa, Yuichi Sano
-
Publication number: 20110309502Abstract: According to one embodiment, a semiconductor device includes a first semiconductor element, a first electrode, a ball part, a second electrode, and a wire. The first electrode is electrically connected to the first semiconductor element. The ball part is provided on the first electrode. The wire connects the ball part and the second electrode. A thickness of a turned-back portion at an end of the wire on a side opposite to the second electrode is smaller than a diameter of the wire.Type: ApplicationFiled: March 21, 2011Publication date: December 22, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Yuichi SANO, Takashi Imoto, Naoto Takebe, Katsuhiro Ishida, Tomomi Honda, Yasushi Kumagai
-
Patent number: 8080120Abstract: A method of manufacturing an annular concentric stranded bead cord, wherein, while rotating an annular core at a fixed position in a peripheral direction, a reel, upon which a lateral wire is wound, repeatedly performs a pendulum swinging movement and a perpendicular movement with respect to the annular core, thereby spirally winding the lateral wire upon the annular core to form a sheath layer. When forming the sheath layer, a fulcrum of the pendulum swinging movement of the reel is determined so that, with reference to a tangential line of a circle of the annular core passing through a winding point where the lateral wire is wound upon the annular core, the lateral wire is wound upon the winding point of the annular core within 15 degrees at a position above the tangential line and within a range of 55 degrees at a position below the tangential line.Type: GrantFiled: December 11, 2007Date of Patent: December 20, 2011Assignees: Sumitomo (SEI) Steel Wire Corp., Sumitomo Electric Tochigi Co., Ltd.Inventors: Yuichi Sano, Hitoshi Wakahara, Kenichi Okamoto
-
Publication number: 20110000533Abstract: It is possible to reduce the contact resistance so as to improve the conversion efficiency of a photoelectric conversion element structure. Provided is a photoelectric conversion element structure of the pin structure which selects an upper limit energy level of the valence band of the p-type semiconductor or the electron affinity of the n-type semiconductor layer and the work function of a metal layer which is brought into contact with the semiconductor, so as to reduce the contact resistance as compared to the case when Al or Ag is used as an electrode. The selected metal layer may be arranged between the electrode formed from Al or Ag and the semiconductor or may be substituted for the n- or p-type semiconductor.Type: ApplicationFiled: March 2, 2009Publication date: January 6, 2011Applicants: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY, TOKYO ELECTRON LIMITEDInventors: Tadahiro Ohmi, Tetsuya Goto, Kouji Tanaka, Yuichi Sano