Patents by Inventor Yuichi Tateyama

Yuichi Tateyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7369008
    Abstract: To provide a MOS varactor in which oscillation frequency variation is small and variation in a capacitance changing voltage is small, and a voltage-controlled oscillator using the MOS varactor, as a load capacitor of an oscillating circuit composed of a feedback resistor 1, an amplifier 2, and a crystal vibrator 3, a variable electrostatic capacitor, which is generated between drain/source terminals and a gate terminal of each of MOS transistors 5a and 6a each of which source and drain terminals are short-circuited, is connected. A bulk terminal of each of the MOS transistors 5a and 6a is connected to one terminal of a resistor 19, a voltage is applied to the other terminal of the resistor 19, the bulk terminal of each of the MOS transistors 5a and 6a is connected to one terminal of a capacitor 20, and the other terminal of the capacitor 20 is grounded.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: May 6, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeo Masai, Yuichi Tateyama, Takashi Otsuka, Hisato Takeuchi
  • Patent number: 7286023
    Abstract: It is an object of the invention to obtain a stable operation with a low phase noise. Moreover, it is another object to obtain an oscillating output which does not cause the delay of a starting time. According to the invention, it is possible to implement a crystal oscillating circuit capable of superposing a signal obtained by feeding back the oscillating output of a crystal oscillating member (10) by a feedback circuit (5) on a control signal for selecting the load capacity of a load capacity selecting portion (3), and influencing an MOS transistor (50) by the voltage noise of the control signal with difficulty, thereby reducing a phase noise, and furthermore, limiting a control signal to be input to the load capacity selecting portion (3) for a certain time in starting and carrying out the starting in a short time.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: October 23, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yuichi Tateyama
  • Patent number: 7283006
    Abstract: An oscillator circuit configured by a feedback resistance 1, an amplifier 2 and a quartz vibrator 3 has a load resistance. MOS transistors 5, 6 short-circuited at source and drain terminals has a capacitance, as a variable capacitance, occurring at between the source-drain terminal and gate terminal. A series connection of DC-cut capacitance 8, 9 and variable capacitance (MOS transistor 5, 6) is configured between one and the other terminals of the quartz vibrator 3 and an AC ground terminal. For example, a threshold voltage control signal for MOS transistor 5, 6 is inputted to the source-drain terminal through a high-frequency removing circuit 10, 11. Meanwhile, a signal that a temperature compensation control signal and an external voltage frequency control signal are superimposed together is inputted to the gate terminal. This makes it possible to desirably determine an output bias to a temperature compensation control circuit and an external voltage frequency control circuit.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: October 16, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yuichi Tateyama
  • Patent number: 7247918
    Abstract: A compact semiconductor device forming a capacitive element for high frequencies that allows good capacitance change to be achieved is provided. AMOS capacitor type semiconductor device includes a gate electrode formed on a surface of a substrate through a gate insulating film, source/drain regions provided to have the gate electrode therebetween, and a back gate including a contact diffusion region for contacting the substrate. Voltage applied across the regions between the source or drain region and the gate electrode and between the gate electrode and the back gate is adjusted, so that charge accumulated at the gate insulating film can be adjusted. In the device, the distance between the source and drain regions or the distance between the back gate and the gate electrode is determined so that electrons or holes can be accumulated at the interface between the gate insulating film and the substrate within a cycle of the applied voltage.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: July 24, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yuichi Tateyama
  • Publication number: 20070126485
    Abstract: To provide a provide a voltage-controlled oscillator capable of controlling the threshold voltage of a MOS transistor independently of a temperature compensation control signal and an external voltage frequency control signal while securing linearity and downsizing the oscillator size without reducing the variable range of frequency, the voltage-controlled oscillator includes an amplifier, a piezoelectric vibrator, and a first load capacitor and a second load capacitor arranged as the load capacitors between both terminals of the piezoelectric vibrator, wherein a capacitor provided as the first load capacitor is composed of a variable capacitor with a small change in capacitance with respect to an input voltage and a capacitor provided as the second load capacitor is composed of a variable capacitor with a large change in capacitance with respect to an input voltage.
    Type: Application
    Filed: November 13, 2006
    Publication date: June 7, 2007
    Inventors: Yuichi Tateyama, Takashi Otsuka
  • Patent number: 7173316
    Abstract: An N type semiconductor layer is epitaxially grown on a P type semiconductor substrate of which one end is grounded, and an element isolation layer made of a P type diffusion layer is formed by means of diffusion around the N type semiconductor layer in order to electrically isolate the N type semiconductor layer. The metal layer which is located above the N type semiconductor layer and which forms a wire or a bonding pad is isolated from the N type semiconductor layer in which a diffusion layer or the like has been formed by an insulating film. An N type buried diffusion layer having an impurity concentration higher than that of the N type semiconductor layer is provided between the P type semiconductor substrate and the N type semiconductor layer. In addition, a P type semiconductor layer is formed by means of diffusion between the insulating film and the N type semiconductor layer plus the element isolation layer.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: February 6, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yuichi Tateyama
  • Publication number: 20060202773
    Abstract: To provide a MOS varactor in which oscillation frequency variation is small and variation in a capacitance changing voltage is small, and a voltage-controlled oscillator using the MOS varactor, as a load capacitor of an oscillating circuit composed of a feedback resistor 1, an amplifier 2, and a crystal vibrator 3, a variable electrostatic capacitor, which is generated between drain/source terminals and a gate terminal of each of MOS transistors 5a and 6a each of which source and drain terminals are short-circuited, is connected. A bulk terminal of each of the MOS transistors 5a and 6a is connected to one terminal of a resistor 19, a voltage is applied to the other terminal of the resistor 19, the bulk terminal of each of the MOS transistors 5a and 6a is connected to one terminal of a capacitor 20, and the other terminal of the capacitor 20 is grounded.
    Type: Application
    Filed: February 27, 2006
    Publication date: September 14, 2006
    Inventors: Shigeo Masai, Yuichi Tateyama, Takashi Otsuka, Hisato Takeuchi
  • Publication number: 20060081892
    Abstract: A compact semiconductor device forming a capacitive element for high frequencies that allows good capacitance change to be achieved is provided. AMOS capacitor type semiconductor device includes a gate electrode formed on a surface of a substrate through a gate insulating film, source/drain regions provided to have the gate electrode therebetween, and aback gate including a contact diffusion region for contacting the substrate. Voltage applied across the regions between the source or drain region and the gate electrode and between the gate electrode and the back gate is adjusted, so that charge accumulated at the gate insulating film can be adjusted. In the device, the distance between the source and drain regions or the distance between the back gate and the gate electrode is determined so that electrons or holes can be accumulated at the interface between the gate insulating film and the substrate within a cycle of the applied voltage.
    Type: Application
    Filed: October 4, 2005
    Publication date: April 20, 2006
    Inventor: Yuichi Tateyama
  • Publication number: 20060071731
    Abstract: An oscillator circuit configured by a feedback resistance 1, an amplifier 2 and a quartz vibrator 3 has a load resistance. MOS transistors 5, 6 short-circuited at source and drain terminals has a capacitance, as a variable capacitance, occurring at between the source-drain terminal and gate terminal. A series connection of DC-cut capacitance 8, 9 and variable capacitance (MOS transistor 5, 6) is configured between one and the other terminals of the quartz vibrator 3 and an AC ground terminal. For example, a threshold voltage control signal for MOS transistor 5, 6 is inputted to the source-drain terminal through a high-frequency removing circuit 10, 11. Meanwhile, a signal that a temperature compensation control signal and an external voltage frequency control signal are superimposed together is inputted to the gate terminal. This makes it possible to desirably determine an output bias to a temperature compensation control circuit and an external voltage frequency control circuit.
    Type: Application
    Filed: October 4, 2005
    Publication date: April 6, 2006
    Inventor: Yuichi Tateyama
  • Publication number: 20050225405
    Abstract: It is an object of the invention to obtain a stable operation with a low phase noise. Moreover, it is another object to obtain an oscillating output which does not cause the delay of a starting time. According to the invention, it is possible to implement a crystal oscillating circuit capable of superposing a signal obtained by feeding back the oscillating output of a crystal oscillating member (10) by a feedback circuit (5) on a control signal for selecting the load capacity of a load capacity selecting portion (3), and influencing an MOS transistor (50) by the voltage noise of the control signal with difficulty, thereby reducing a phase noise, and furthermore, limiting a control signal to be input to the load capacity selecting portion (3) for a certain time in starting and carrying out the starting in a short time.
    Type: Application
    Filed: March 3, 2004
    Publication date: October 13, 2005
    Inventor: Yuichi Tateyama
  • Publication number: 20050098849
    Abstract: An N type semiconductor layer is epitaxially grown on a P type semiconductor substrate of which one end is grounded, and an element isolation layer made of a P type diffusion layer is formed by means of diffusion around the N type semiconductor layer in order to electrically isolate the N type semiconductor layer. The metal layer which is located above the N type semiconductor layer and which forms a wire or a bonding pad is isolated from the N type semiconductor layer in which a diffusion layer or the like has been formed by an insulating film. An N type buried diffusion layer having an impurity concentration higher than that of the N type semiconductor layer is provided between the P type semiconductor substrate and the N type semiconductor layer. In addition, a P type semiconductor layer is formed by means of diffusion between the insulating film and the N type semiconductor layer plus the element isolation layer.
    Type: Application
    Filed: December 6, 2004
    Publication date: May 12, 2005
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Yuichi Tateyama
  • Patent number: 6292066
    Abstract: A temperature compensating crystal oscillation device includes a constant voltage circuit (12) for outputting a predetermined voltage independent of the ambient temperature, a temperature sensor circuit (13) for outputting a voltage in proportion to the ambient temperature, and a control circuit (14) for receiving the constant voltage output from the constant voltage circuit (12) and the voltage output in proportion to the temperature from the temperature sensor circuit (13) and for generating a control voltage (Vc) used for compensating a temperature characteristic of a quartz oscillator in the entire range of the ambient temperature through polygonal lines approximation of a negative cubic curve by using continuous lines.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: September 18, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shuji Shibuya, Hisato Takeuchi, Junichi Matsuura, Yuichi Tateyama, Takaharu Saeki
  • Patent number: D280650
    Type: Grant
    Filed: September 16, 1983
    Date of Patent: September 17, 1985
    Assignee: Kawada Co., Ltd.
    Inventor: Yuichi Tateyama