Abstract: An information processing apparatus includes a first system and a second system. The first system includes a CPU capable of executing an operating system, a first display controller that causes a display device to display data, a peripheral device having an interface and being capable of outputting image data via the interface, and a first controller that executes communication with the peripheral device via the interface and receives the image data output from the peripheral device. The second system includes a second controller that executes communication with the peripheral device via the interface and receives the image data output from the peripheral device, a second display controller that causes the display device to display the image data, which is received by the second controller, and a switch device that switches a destination of connection of the interface of the peripheral device from the first controller to the second controller.

Abstract: An information processing apparatus includes a first system and a second system. The first system includes a CPU capable of executing an operating system, a first display controller that causes a display device to display data, a peripheral device having an interface and being capable of outputting image data via the interface, and a first controller that executes communication with the peripheral device via the interface and receives the image data output from the peripheral device. The second system includes a second controller that executes communication with the peripheral device via the interface and receives the image data output from the peripheral device, a second display controller that causes the display device to display the image data, which is received by the second controller, and a switch device that switches a destination of connection of the interface of the peripheral device from the first controller to the second controller.

Abstract: When a power button is pressed, an embedded controller (EC) first starts an operating system which is function limited but short in starting time on a first system having a CPU. After that, upon receiving a request to use multifunctional software, the EC starts an operating system which is multifunctional but long in starting time on a second system having a CPU, thus switching between the operating systems to allow selective use thereof.

Abstract: A register group (REG) is constructed by a register for calendar data of year, month, date, hour, minute and second, a data register constructed by an empty area, for storing alarm time of month, date, hour, minute and second, and a register for controlling generation of various interrupts. A comparator compares calendar information of month, date, hour, minute and second of the present time with month, date, hour, minute and second of set alarm time and an interrupt is generated when the compared values coincide with each other.

Abstract: When a full-color display is to be performed, the upper 4-bit data of each of R, G, and B video data each having an 8-bit width is used as video data of a TFT type LCD in which a full-color display is to be performed, and the lower 4-bit data is supplied to a frame rate controller (36) arranged to control an STN type LCD. For this reason, 16 gray scale levels expressed by the upper 4-bit data are combined to 16 gray scale levels expressed by the frame rate controller (36), and each of R, G, and B video data can be emulatively expressed on the 16-gray-scale TFT type LCD in 256 gray scale levels. When the frame rate controller (36) is used for a full-color emulation, the full-color display can be realized without increasing the number of circuits.

Abstract: During a vertical blank period, in order to prevent generation of noise lines, a display controller outputs the same video data FVD as that of a display final line as dummy data of a vertical blank period start line, and outputs, in advance, video data to be displayed on a display start line in the next frame cycle as dummy data of a vertical blank period final line. The display controller also output a shift clock together with these dummy data. As a result, both upon a change from the display period to the vertical blank period and upon a change from the vertical blank period to the display period, a video data value difference can be eliminated, and generation of noise lines can be prevented.

Abstract: In the interlocking mode, the color of the color data is converted into a brightness value by a brightness converting circuit in accordance with the value of each of R, G, B of the color data written into each color register of RAMDAC. Gradation data to be written into each register of the flat palette table is formed from the brightness value. In the non-interlocking mode, an optional gradation data irrelevant to the color data of the RAMDAC is written into each register of the flat palette table. By the switching between interlocking and non-interlocking modes, selection can be made between the monochrome gradation display which faithfully reproduces the color display screen of a CRT display and the monochrome display of an optional gradation irrelevant to the color display screen.

Abstract: When a display control apparatus displays an 8-bit graphics data item and a 4-bit text data item, superimposed upon each other, on a display device which has pixels each having two dots it outputs, for one of the two dots an 8-bit text data item obtained by combining the 4-bit text data item with a 4-bit fixed data item, and outputs the 8-bit graphics data item for the other of the two dots. The display control apparatus has a multiplexer for outputting in order the upper 4 bits and lower 4 bits of the 8-bit graphics data item, each time a time period for displaying one dot elapses, a delaying circuit connected to the multiplexer, for generating delayed data items FG1 and FG2 by delaying the output GX of the multiplexer by a time period for displaying one dot and by a time period for displaying two dots, respectively, and a selection/output circuit.

Abstract: A CRT display unit and a flat panel type display unit are switched for use in a computer system. Both the CRT display unit and the flat panel type display unit display an image stored in an image memory in accordance with display parameters set in an I/O register. A parameter memory stores a set of display parameters for each of display modes of the CRT display unit and the flat display unit. When switching between the display units is requested via a keyboard, transfer control means transfers display parameters for the newly designated display unit from the parameter memory to the I/O register. A display circuit causes the newly designated display unit to display an image in accordance with the display parameters stored in the I/O register and the image data.