Patents by Inventor Yuichi Urano
Yuichi Urano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9666437Abstract: A method for manufacturing a semiconductor device including a semiconductor chip having a front surface electrode and a rear surface electrode provided on a front surface and a rear surface, respectively, the method includes a front surface electrode layer forming step of forming a front surface electrode layer as the front surface electrode on a front surface of a semiconductor wafer forming the semiconductor chip; a thinning step of grinding a rear surface of the semiconductor wafer to reduce a thickness of the semiconductor wafer after the front surface electrode layer forming step; a plating step of forming an electrode plating film as the front surface electrode on a surface of the front surface electrode layer after the thinning step; and a rear surface electrode forming step of forming the rear surface electrode on the ground rear surface of the semiconductor wafer after the plating step.Type: GrantFiled: October 8, 2015Date of Patent: May 30, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventor: Yuichi Urano
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Publication number: 20160027648Abstract: A method for manufacturing a semiconductor device including a semiconductor chip having a front surface electrode and a rear surface electrode provided on a front surface and a rear surface, respectively, the method includes a front surface electrode layer forming step of forming a front surface electrode layer as the front surface electrode on a front surface of a semiconductor wafer forming the semiconductor chip; a thinning step of grinding a rear surface of the semiconductor wafer to reduce a thickness of the semiconductor wafer after the front surface electrode layer forming step; a plating step of forming an electrode plating film as the front surface electrode on a surface of the front surface electrode layer after the thinning step; and a rear surface electrode forming step of forming the rear surface electrode on the ground rear surface of the semiconductor wafer after the plating step.Type: ApplicationFiled: October 8, 2015Publication date: January 28, 2016Inventor: Yuichi URANO
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Publication number: 20140252265Abstract: The present invention relates to a thermoplastic moulding composition, comprising at least one thermoplastic polymer A); at least one heat conducting filler B); and at least one halogen-containing flame retardant C). Moreover, the invention relates to the use of the inventive moulding compositions for production of fibers, films or mouldings, to the resultant mouldings and to the use thereof for heat transport.Type: ApplicationFiled: March 7, 2014Publication date: September 11, 2014Applicant: BASF SEInventors: Claus Gabriel, Yuichi Urano, Alexander König, Kwee Heong Dennis Chern, Gaurav Ramanlal Kasaliwal
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Patent number: 8709912Abstract: Even when a substrate for treatment is joined with a supporting substrate having an outer shape larger than that of the substrate for treatment, with a photothermal conversion layer and an adhesive layer interposed, and the surface of the substrate for treatment on the side opposite this joined surface is treated, the occurrence of a defective external appearance on the treatment surface of the substrate for treatment is prevented. An adhesive layer 4 is formed on one surface of a substrate for treatment 3, a photothermal conversion layer 2 is formed on one surface of a supporting substrate 1 having a surface with an outer shape larger than that of the surface of the substrate for treatment, and the substrate for treatment 3 is bonded onto the surface of the photothermal conversion layer 2 with the adhesive layer 4 interposed, to obtain a layered member.Type: GrantFiled: April 15, 2009Date of Patent: April 29, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Yuichi Urano, Kenichi Kazama
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Patent number: 8518804Abstract: A semiconductor device manufacturing method and manufacturing apparatus with which it is possible, when a wafer has a warp, to effectively peel off an ultraviolet peelable tape with ultraviolet irradiation of a short duration. Even when a wafer has a warp, by correcting the warp of the wafer with an ultraviolet transmitting plate, and uniformly irradiating an ultraviolet peelable tape attached to the wafer with ultraviolet light, it is possible to reduce a distance between an ultraviolet light source and the ultraviolet peelable tape. Also, by blocking heat from the ultraviolet light source with the ultraviolet transmitting plate, it is possible to suppress a rise in temperature of the wafer. As a result of this, it is possible to effectively peel the ultraviolet peelable tape from the wafer with ultraviolet irradiation of a short duration without any adhesive residue remaining.Type: GrantFiled: October 20, 2011Date of Patent: August 27, 2013Assignee: Fuji Electric Co., Ltd.Inventor: Yuichi Urano
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Patent number: 8492256Abstract: A method of manufacturing a semiconductor apparatus includes forming back surface electrode 4 on back surface of semiconductor wafer 20, that bends convexly toward the front surface side due to back surface electrode 4 being formed; treating the back surface with a plasma for removing the deposits on the back surface; sticking removable adhesive tape 23 to the back surface along the warp thereof for maintaining the bending state of semiconductor wafer 20 after the step of sticking; electrolessly plating to form film 26 on the front surface of semiconductor wafer 20; peeling off removable adhesive tape 23; cutting out semiconductor chips; and mounting the semiconductor chip by bonding with a solder for manufacturing a semiconductor apparatus. The manufacturing method prevents external appearance anomalies from occurring on the back surface electrode, improves the reliability, and allows manufacture of the semiconductor apparatuses with a high throughput of non-defective products.Type: GrantFiled: April 12, 2011Date of Patent: July 23, 2013Assignee: Fuji Electric Co., Ltd.Inventor: Yuichi Urano
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Patent number: 8198104Abstract: A method of manufacturing a semiconductor device on a semiconductor substrate, includes the steps of forming a first metal film on a front surface of the semiconductor substrate; forming a second metal film on the surface of the first metal film; activating a surface of the second metal film to provide an activated surface; and forming a plated film on the activated surface by a wet plating method in a plating bath that includes a reducing agent that is oxidized during plating and that has a rate of oxidation, wherein the second metal film is a metal film mainly composed of a first substance that enhances the rate of oxidation of the reducing agent in the plating bath. Wet plating is preferably an electroless process.Type: GrantFiled: March 22, 2010Date of Patent: June 12, 2012Assignee: Fuji Electric Co., Ltd.Inventors: Yuichi Urano, Takayasu Horasawa
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Publication number: 20120100639Abstract: A semiconductor device manufacturing method and manufacturing apparatus with which it is possible, when a wafer has a warp, to effectively peel off an ultraviolet peelable tape with ultraviolet irradiation of a short duration. Even when a wafer has a warp, by correcting the warp of the wafer with an ultraviolet transmitting plate, and uniformly irradiating an ultraviolet peelable tape attached to the wafer with ultraviolet light, it is possible to reduce a distance between an ultraviolet light source and the ultraviolet peelable tape. Also, by blocking heat from the ultraviolet light source with the ultraviolet transmitting plate, it is possible to suppress a rise in temperature of the wafer. As a result of this, it is possible to effectively peel the ultraviolet peelable tape from the wafer with ultraviolet irradiation of a short duration without any adhesive residue remaining.Type: ApplicationFiled: October 20, 2011Publication date: April 26, 2012Applicant: FUJI ELECTRIC CO., LTD.Inventor: Yuichi URANO
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Publication number: 20110256668Abstract: A method of manufacturing a semiconductor apparatus includes forming back surface electrode 4 on back surface of semiconductor wafer 20, that bends convexly toward the front surface side due to back surface electrode 4 being formed; treating the back surface with a plasma for removing the deposits on the back surface; sticking removable adhesive tape 23 to the back surface along the warp thereof for maintaining the bending state of semiconductor wafer 20 after the step of sticking; electrolessly plating to form film 26 on the front surface of semiconductor wafer 20; peeling off removable adhesive tape 23; cutting out semiconductor chips; and mounting the semiconductor chip by bonding with a solder for manufacturing a semiconductor apparatus. The manufacturing method prevents external appearance anomalies from occurring on the back surface electrode, improves the reliability, and allows manufacture of the semiconductor apparatuses with a high throughput of non-defective products.Type: ApplicationFiled: April 12, 2011Publication date: October 20, 2011Applicant: FUJI ELECTRIC CO., LTD.Inventor: Yuichi URANO
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Publication number: 20110129989Abstract: Even when a substrate for treatment is joined with a supporting substrate having an outer shape larger than that of the substrate for treatment, with a photothermal conversion layer and an adhesive layer interposed, and the surface of the substrate for treatment on the side opposite this joined surface is treated, the occurrence of a defective external appearance on the treatment surface of the substrate for treatment is prevented. An adhesive layer 4 is formed on one surface of a substrate for treatment 3, a photothermal conversion layer 2 is formed on one surface of a supporting substrate 1 having a surface with an outer shape larger than that of the surface of the substrate for treatment, and the substrate for treatment 3 is bonded onto the surface of the photothermal conversion layer 2 with the adhesive layer 4 interposed, to obtain a layered member.Type: ApplicationFiled: April 15, 2009Publication date: June 2, 2011Applicant: FUJI ELECTRIC SYSTEMS CO. LTD.Inventors: Yuichi Urano, Kenichi Kazama
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Patent number: 7947586Abstract: A method of manufacturing a semiconductor device is disclosed, wherein a plating layer is formed on a first surface side of a semiconductor substrate stably and at a low cost, while preventing the plating liquid from being contaminated and avoiding deposition of uneven plating layer on a second surface side. An electrode is formed on the first surface of the semiconductor substrate, and another electrode is formed on the second surface. A curing resin is applied on the electrode on the second surface and a film is stuck on the curing resin, and the curing resin is then cured. After that, a plating process is conducted on the first surface. The film and the curing resin are then peeled off.Type: GrantFiled: February 4, 2010Date of Patent: May 24, 2011Assignee: Fuji Electric Systems Co., Ltd.Inventor: Yuichi Urano
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Publication number: 20100240213Abstract: A method of manufacturing a semiconductor device on a semiconductor substrate, includes the steps of forming a first metal film on a front surface of the semiconductor substrate; forming a second metal film on the surface of the first metal film; activating a surface of the second metal film to provide an activated surface; and forming a plated film on the activated surface by a wet plating method in a plating bath that includes a reducing agent that is oxidized during plating and that has a rate of oxidation, wherein the second metal film is a metal film mainly composed of a first substance that enhances the rate of oxidation of the reducing agent in the plating bath. Wet plating is preferably an electroless process.Type: ApplicationFiled: March 22, 2010Publication date: September 23, 2010Applicant: FUJI ELECTRIC SYSTEMS CO., LTD.Inventors: Yuichi Urano, Takayasu Horasawa
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Publication number: 20100197127Abstract: A method of manufacturing a semiconductor device is disclosed, wherein a plating layer is formed on a first surface side of a semiconductor substrate stably and at a low cost, while preventing the plating liquid from being contaminated and avoiding deposition of uneven plating layer on a second surface side. An electrode is formed on the first surface of the semiconductor substrate, and another electrode is formed on the second surface. A curing resin is applied on the electrode on the second surface and a film is stuck on the curing resin, and the curing resin is then cured. After that, a plating process is conducted on the first surface. The film and the curing resin are then peeled off.Type: ApplicationFiled: February 4, 2010Publication date: August 5, 2010Applicant: FUJI ELECTRIC SYSTEMS CO., LTD.Inventor: Yuichi URANO
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Patent number: 6121097Abstract: A polysilicon film is deposited in a trench formed in a silicon element substrate. The polysilicon film in the trench and on the silicon element substrate is anisotropically etched, so that the film remains on the side wall of the trench. The polysilicon film on the side wall is oxidized to obtain an insulating film, which buries the trench. At the same time, an oxidized film is formed on the surface of the silicon element substrate to complete a trench-mold separation area.Type: GrantFiled: May 5, 1998Date of Patent: September 19, 2000Assignee: Fuji Electric Co., Ltd.Inventors: Yuichi Urano, Masato Nishizawa, Yoshiyuki Sakai, Naoki Ito, Shinichi Hashimoto
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Patent number: 5854120Abstract: A polysilicon film is deposited in a trench formed in a silicon element substrate. The polysilicon film in the trench and on the silicon element substrate is anisotropically etched, so that the film remains on the side wall of the trench. The polysilicon film on the side wall is oxidized to obtain an insulating film, which buries the trench. At the same time, an oxidized film is formed on the surface of the silicon element substrate to complete a trench-mold separation area.Type: GrantFiled: December 17, 1996Date of Patent: December 29, 1998Assignee: Fuji Electric Co.Inventors: Yuichi Urano, Masato Nishizawa, Yoshiyuki Sakai, Naoki Ito, Shinichi Hashimoto
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Patent number: 5576986Abstract: A highly reliable memory device with excellent heat resistance that can be used in any environment utilizes a chemical change to define a state transition. The memory device includes a micro vacuum tube structure having a recess portion formed on an upper face of a quartz substrate, a cold cathode having many comb-tooth like tips extending from the quartz substrate over to one side of the recess portion, a rectangular control electrode disposed on the side of the cold cathode at the bottom of the recess portion, an anode extending from the quartz substrate over to the other side of the recess portion and facing opposed to the cold cathode, and a sealing member for vacuum sealing a space inside the recess portion 11a. N.sub.2 and O.sub.2 gases are enclosed in a space under the pressure of 0.2 mmHg. By changing the control electrode voltage, energy of accelerated electrons is changed: NO is produced at the control voltage of 17 eV, NO2 at 23 eV and the product gases dissociate to N.sub.2 and O.sub.Type: GrantFiled: October 14, 1994Date of Patent: November 19, 1996Assignee: Fuji Electric Co. Ltd.Inventors: Kazuo Matsuzaki, Yoshiyuki Sakai, Yuichi Urano, Hidekatsu Kuroda, Akira Amano