Abstract: A data relay apparatus in which a search request command can be inputted efficiently to a content addressable/associative memory device. When a packet is inputted, a network processor generates a search request and passes it to the content addressable/associative memory device. Then the content addressable/associative memory device analyzes the structure of the search request and generates a plurality of search conditions. The content addressable/associative memory device makes a search according to each search condition and outputs a memory address corresponding to a detected piece of information to be searched to a memory device. The memory device passes a candidate search result corresponding to the memory address to the network processor as a search result.

Abstract: In a method and device for retrieving data matching a retrieval key from a database, entries having all of unmasked bits in all of retrieved fields matched with data bits of retrieval keys corresponding to the unmasked bits are determined to be an interim retrieval result from among entries divided into a plurality of fields and stored in a database; a longest prefix length for each of the retrieved fields is obtained from among prefix lengths of the retrieved fields of the interim retrieval result; and an entry in the interim retrieval result having the longest prefix length in one of the retrieved fields whose priority is the highest is determined to be a retrieval result.

Abstract: A data relay apparatus in which a search request command can be inputted efficiently to a content addressable/associative memory device. When a packet is inputted, a network processor generates a search request and passes it to the content addressable/associative memory device. Then the content addressable/associative memory device analyzes the structure of the search request and generates a plurality of search conditions. The content addressable/associative memory device makes a search according to each search condition and outputs a memory address corresponding to a detected piece of information to be searched to a memory device. The memory device passes a candidate search result corresponding to the memory address to the network processor as a search result.

Abstract: A plurality of types of search data, such as IP addresses and port numbers are input collectively, the thus-input data is divided according to the relevant bit lengths, and, then, the divided items of data are provided to relevant entry tables. Thereby, issuance of search request from a processor to the search device, i.e., CAM device should be made only once. Then, search is made on each item of search data individually, and, as a result, the search result therefor is obtained from a respective one of the entry tables.

Abstract: An associative memory apparatus has such a structure as to reduce a load of an updating work and readily cope with an increase of the capacity. The associative memory apparatus outputs longest prefix match in only one searching operation, thereby shortening a processing time for the searching process. The apparatus comprises entry units, each of which includes a logical operating means outputting information about a bit length not masked in entry data when the entry data stored in its own entry unit coincides with bit data that is a key, and a search result outputting means outputting a search match information with respect to the search key only when the entry data stored in its own entry unit is entry data having the longest bit length not masked.

Abstract: An associative memory apparatus has such a structure as to reduce a load of an updating work and readily cope with an increase of the capacity. The associative memory apparatus outputs longest prefix match in only one searching operation, thereby shortening a processing time for the searching process. The apparatus comprises entry units, each of which includes a logical operating means outputting information about a bit length not masked in entry data when the entry data stored in its own entry unit coincides with bit data that is a key, and a search result outputting means outputting a search match information with respect to the search key only when the entry data stored in its own entry unit is entry data having the longest bit length not masked.

Abstract: A semiconductor memory selects desired one of word lines, which belong to banks each including a memory cell array, on the basis of a main WD select signal (mwd) and sub-WD select signals (swdx and swdz) determined in accordance with an address. The main WD select signal is a pulse signal. A latch circuit latches, for a predetermined time, the state of the sub-WD select signals having changed on the basis of state changes of the main WD select signal. This allows the banks to share the main WD select signal. Since a main WD signal generator is thus shared by the banks, the area of a chip can be reduced.

Abstract: A semiconductor memory selects desired one of word lines, which belong to banks each including a memory cell array, on the basis of a main WD select signal (mwd) and sub-WD select signals (swdx and swdz) determined in accordance with an address. The main WD select signal is a pulse signal. A latch circuit latches, for a predetermined time, the state of the sub-WD select signals having changed on the basis of state changes of the main WD select signal. This allows the banks to share the main WD select signal. Since a main WD signal generator is thus shared by the banks, the area of a chip can be reduced.

Abstract: A semiconductor memory has memory cells arranged in arrays, direct-type sense amplifiers arranged in each column of the memory cells, for writing and reading data to and from a memory cell to be accessed, column selection lines for selecting sense amplifiers that are in a column that involves the memory cell to be accessed, write-only column selection lines for selecting sense amplifiers that are in a row that involves the memory cell to be accessed if the memory cell is accessed to write data thereto, and local drivers. The sense amplifiers are grouped, in each row, into sense amplifier blocks. The write-only column selection lines consist of first selection lines for selecting sense amplifier blocks that are in the row that involves the memory cell to be accessed for data write and second selection lines for selecting sense amplifiers that are contained in the selected sense amplifier blocks.

Abstract: As the pre-charge potential for write global data buses (12, 13), a potential lower than the power supply voltage (Vii) for peripheral circuit by the threshold voltage (Vth) of a transistor is used. This suppresses disturbance in the potential of a pair of bit lines (18, 19) due to pre-charge operation. It suffices if the write global data buses are pre-charged to the potential lower than the power supply voltage (Vii) for peripheral circuit by the threshold voltage (Vth). This can reduce current consumption accordingly. By generating the pre-charge potential without using the power supply voltage (Viic) for core, adverse effects on sense operation can be avoided.

Abstract: In a semiconductor integrated circuit having the function of executing a pre-charge operation of a data bus when data is transferred to the data bus from a plurality of driver circuits connected to the data bus, a reset circuit for executing the pre-charge operation of the data bus is constituted so as to start the pre-charge operation of the data bus upon receiving an end timing of a strobe signal. Preferably, the reset circuit detects that the data bus reaches a pre-charge level for executing the pre-charge operation, and then terminates the pre-charge operation. On the other hand, in a semiconductor integrated circuit having a data latch function by a pipeline system when the data is read out from a memory cell, etc.

Abstract: In a data bus amplifier activation method for a semiconductor memory device having a memory cell array, a column selection circuit for selecting a column in the memory cell array, a read data bus for transferring read data, output from the column selected by the column selection circuit, to a read data bus amplifier, and a write data bus for transferring write data, output from a write data bus amplifier, to the column selected by the column selection circuit, the read data bus amplifier or the write data bus amplifier is activated by detecting the selection of the column effected by the column selection circuit.