Abstract: A substrate processing system includes a substrate processing apparatus including a processing container and a boat for transferring a plurality of substrates into the processing container; a measuring device that measures a substrate processing result of a substrate in the substrate processing apparatus; and an information processing device that estimates substrate processing results at a plurality of points on the substrate, based on the substrate processing result. The information processing device of the substrate processing system includes an input unit that inputs summary data extracted from the substrate processing result measured by the measuring device, a calculation unit that calculates a plurality of estimated values indicating the substrate processing results at the plurality of points on the substrate based on the summary data; and a display control unit that displays the plurality of estimated values on a display device.

Abstract: A display device with high display quality is provided. The display device includes a first light-emitting device, a second light-emitting device, and an insulating layer. The first light-emitting device includes a first pixel electrode, a first EL layer, and a common electrode. The second light-emitting device includes a second pixel electrode, a second EL layer, and the common electrode. The insulating layer includes an opening, and includes a first surface in contact with a side surface of the first pixel electrode, a second surface facing the first surface, and a third surface in contact with a bottom surface of the first EL layer. The insulating layer includes a region where the third surface and the top surface of the first pixel electrode are level or substantially level with each other. In a cross-sectional view, an angle formed between the second surface and the third surface is greater than or equal to 80° and less than or equal to 110°.

Abstract: A transistor with high electrical characteristics is provided. A transistor with a high on-state current is provided. A transistor with small parasitic capacitance is provided. A transistor, a semiconductor device, or a memory device which can be miniaturized or highly integrated is provided. The transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer over the semiconductor layer, and a gate electrode over the gate insulating layer. A first insulating layer is between the first conductive layer and the second conductive layer. The second conductive layer is over the first insulating layer. The first insulating layer and the second conductive layer include an opening portion reaching the first conductive layer. The semiconductor layer is in contact with a sidewall of the opening portion. The semiconductor layer includes a first oxide layer and a second oxide layer. The first oxide layer includes a first region and a second region.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a first conductor, a second conductor, a third oxide, a fourth oxide, and a second insulator over the second oxide; a third insulator over the first conductor, the second conductor, the third oxide, and the fourth oxide; a fourth insulator over the second insulator; and a third conductor over the fourth insulator. The second insulator is positioned between the first conductor and the second conductor. The third oxide is positioned between the first conductor and the second insulator. The fourth oxide is positioned between the second conductor and the second insulator. The thickness of the third oxide between the first conductor and the second insulator is greater than or equal to 3 nm and less than or equal to 8 nm.

Abstract: A semiconductor device with little variation in transistor characteristics is provided. First to third oxide films, a first conductive film, a first insulating film, and a second conductive film are sequentially formed. Shaping them into island-like shapes. An insulator is formed over the island-like shapes and an opening is formed in the insulator and a part of the island-like shapes. Another oxide film, a gate insulating film, and a gate electrode are formed in the opening in this order to form the transistor.

Abstract: A method of fabricating a display device with high resolution is provided. A display device having both high display quality and high resolution is provided. The method of fabricating a display device includes steps of forming a first EL film and a first sacrificial film over a first pixel electrode and a second pixel electrode; etching the first sacrificial film to form a first sacrificial layer; etching the first EL film to form a first EL layer and to expose the second pixel electrode; forming a second EL film and a second sacrificial film; etching the second sacrificial film to form a second sacrificial layer; etching the second EL film to form a second EL layer; forming an insulating film covering the first sacrificial layer, the first EL layer, the second sacrificial layer, and the second EL layer; and etching the insulating film to form an insulating layer including a region in contact with a side surface of the first EL layer and a region in contact with a side surface of the second EL layer.

Abstract: A highly reliable display device is provided. The display device includes a first light-emitting element and a second light-emitting element adjacent to the first light-emitting element. The first light-emitting element includes a first pixel electrode, a first EL layer over the first pixel electrode, and a common electrode over the first EL layer, and the second light-emitting element includes a second pixel electrode, a second EL layer over the second pixel electrode, and the common electrode over the second EL layer. An end portion of the first pixel electrode and an end portion of the second pixel electrode each have a tapered shape. The first EL layer covers the end portion of the first pixel electrode, and the second EL layer covers the end portion of the second pixel electrode. The first EL layer includes a region with a thickness less than or equal to 150 nm.

Abstract: A flush toilet includes a bowl part, a drainage water trap part that is connected to a bottom part of the bowl part, and a water drainage socket that is connected to the drainage water trap part and includes an upper side water drainage socket that extends downward from the drainage water trap part, a back side R part that is connected to the upper side water drainage socket and changes a flow channel so that a washing water that flows from an upper side is directed to a front side, and a horizontal pipe that extends forward from the back side R part. The back side R part and the horizontal pipe include a water storage part that stores a part of washing water. The water storage part is arranged on a lower side of a back side lower end part of the drainage water trap part.

Abstract: A liquid cosmetic composition which provides easily a clear and brilliant coating film without causing flaky pigments to be overlapped on each other when the liquid cosmetic composition containing a small amount of brilliant flaky pigments is filled in an applicator having a coating part composed of a brush to be coated on a surface such as a skin. The liquid cosmetic composition of the present invention is characterized in containing at least 0.01 to 10 mass % of a flaky pigment coated on a surface with a compound selected from the following A group, 0.05 to 5 mass % of layered clay mineral particles, 1 to 20 mass % of an acrylic copolymer in terms of a solid content and water and being filled in an applicator provided with a coating part having a brush: A group: cellulose, hemicellulose, lignin, chitin, chitosan.

Abstract: Provided is a liquid cosmetic composition which provides easily a clear and brilliant coating film without causing flaky pigments to be overlapped on each other when the liquid cosmetic composition containing a small amount of brilliant flaky pigments is filled in an applicator having a coating part composed of a brush to be coated on a surface such as a skin. The liquid cosmetic composition of the present invention is characterized in containing at least 0.01 to 10 mass % of a flaky pigment coated on a surface with a compound selected from the following A group, 0.05 to 5 mass % of layered clay mineral particles, 1 to 20 mass % of an acrylic copolymer in terms of a solid content and water and being filled in an applicator provided with a coating part having a brush: A group: cellulose, hemicellulose, lignin, chitin, chitosan.

Abstract: In order to prevent an application fluid from staining the skin surface when the application fluid is applied, a hair dye container includes a container storing a hair dyeing fluid and a grip, integrated with an application body, and being be attachable to and detachable from the container. The application body includes a fin section having multiple fins arranged at intervals, multiple combs having an outer diameter of at least 1 mm larger than the outer diameter of the fins, and an axial core having the fin section provided around the core to retain the a dyeing fluid by capillary action between the fins, some or several fins being interposed between the combs.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

Abstract: A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film.

Abstract: A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

Abstract: A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

Abstract: There is a vehicle operation system (300) which includes a driving operating elements (302) that receive an operation of a driver for acceleration and deceleration or steering of a vehicle, and a control unit (301) that controls holding mechanisms (303) such that the driving operating elements are stored with a change in state of the holding mechanisms on the basis of an execution state of automated driving executed in a vehicle.

Abstract: A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film.

Abstract: A graphene wiring structure of an embodiment has a multilayered graphene having a plurality of planar graphene sheets laminated, and a first interlayer substance being a metal oxyhalide between the plurality of planar graphene sheets.