Patents by Inventor Yuichi Yamazaki

Yuichi Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250049649
    Abstract: An aqueous liquid cosmetic material suitable for makeup cosmetic materials for eyeshadows, eyeliners, eyebrow makeup, mascaras, and the like that, even when containing a larger amount of a flaky pigment such as a glittering pigment than the known ones and made into a low-viscosity aqueous blending composition, can still greatly improve the intensity of lines drawn using the cosmetic material without causing aggregation or settling of the flaky pigment while also achieving an improved adhering property. The aqueous liquid cosmetic material is a cosmetic material accommodated in a pen-type applicator A having a brush 23 at an application portion, the aqueous liquid cosmetic material containing at least a flaky pigment A, 1 to 9 mass % of a flaky pigment B that is surface-treated with at least one type of crystalline cellulose, a dextrin, a thickening polysaccharide, emulsion particles containing 4 to 10 mass % of an acrylate copolymer in terms of solid content, and water.
    Type: Application
    Filed: December 23, 2022
    Publication date: February 13, 2025
    Applicant: MITSUBISHI PENCIL COMPANY, LIMITED
    Inventors: Ryuichi SHINOHARA, Yuichi YAMAZAKI
  • Patent number: 12224293
    Abstract: A semiconductor device including: a first insulator in which an opening is formed; a first conductor positioned in the opening; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide and a fourth oxide over the second oxide; a second conductor over the third oxide and the first conductor; a third conductor over the fourth oxide; a fifth oxide over the second oxide; a second insulator over the fifth oxide; and a fourth conductor positioned over the second insulator and overlapping with the fifth oxide. The fifth oxide is in contact with each of a side surface of the third oxide and a side surface of the fourth oxide. The conductivity of the third oxide is higher than the conductivity of the second oxide. The second conductor is in contact with the top surface of the first conductor.
    Type: Grant
    Filed: December 29, 2023
    Date of Patent: February 11, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuichi Sato, Hitoshi Nakayama
  • Publication number: 20250046658
    Abstract: A substrate processing method includes providing a substrate processing apparatus including a processing container that accommodates a substrate, and a heater that heats an inside of the processing container; setting a specific section with an in-plane temperature distribution of a substrate that results in a desired outcome of substrate processing based on a first prediction model that predicts a time-dependent change of the in-plane temperature distribution of the substrate after temperature increase or decrease caused by the heater; and performing the substrate processing in the specific section.
    Type: Application
    Filed: July 24, 2024
    Publication date: February 6, 2025
    Inventors: Hiroyuki KARASAWA, Masakazu YAMAMOTO, Yuichi TAKENAGA, Youngtai KANG, Shota YAMAZAKI
  • Patent number: 11890363
    Abstract: A liquid cosmetic composition which provides easily a clear and brilliant coating film without causing flaky pigments to be overlapped on each other when the liquid cosmetic composition containing a small amount of brilliant flaky pigments is filled in an applicator having a coating part composed of a brush to be coated on a surface such as a skin. The liquid cosmetic composition of the present invention is characterized in containing at least 0.01 to 10 mass % of a flaky pigment coated on a surface with a compound selected from the following A group, 0.05 to 5 mass % of layered clay mineral particles, 1 to 20 mass % of an acrylic copolymer in terms of a solid content and water and being filled in an applicator provided with a coating part having a brush: A group: cellulose, hemicellulose, lignin, chitin, chitosan.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: February 6, 2024
    Assignee: MITSUBISHI PENCIL COMPANY, LIMITED
    Inventors: Satoshi Sakuma, Yuichi Yamazaki
  • Publication number: 20220265534
    Abstract: Provided is a liquid cosmetic composition which provides easily a clear and brilliant coating film without causing flaky pigments to be overlapped on each other when the liquid cosmetic composition containing a small amount of brilliant flaky pigments is filled in an applicator having a coating part composed of a brush to be coated on a surface such as a skin. The liquid cosmetic composition of the present invention is characterized in containing at least 0.01 to 10 mass % of a flaky pigment coated on a surface with a compound selected from the following A group, 0.05 to 5 mass % of layered clay mineral particles, 1 to 20 mass % of an acrylic copolymer in terms of a solid content and water and being filled in an applicator provided with a coating part having a brush: A group: cellulose, hemicellulose, lignin, chitin, chitosan.
    Type: Application
    Filed: July 8, 2020
    Publication date: August 25, 2022
    Applicant: MITSUBISHI PENCIL COMPANY, LIMITED
    Inventors: Satoshi SAKUMA, Yuichi YAMAZAKI
  • Publication number: 20210093068
    Abstract: In order to prevent an application fluid from staining the skin surface when the application fluid is applied, a hair dye container includes a container storing a hair dyeing fluid and a grip, integrated with an application body, and being be attachable to and detachable from the container. The application body includes a fin section having multiple fins arranged at intervals, multiple combs having an outer diameter of at least 1 mm larger than the outer diameter of the fins, and an axial core having the fin section provided around the core to retain the a dyeing fluid by capillary action between the fins, some or several fins being interposed between the combs.
    Type: Application
    Filed: September 30, 2020
    Publication date: April 1, 2021
    Inventors: Shoichi SAITO, Yuichi YAMAZAKI
  • Patent number: 10741443
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: August 11, 2020
    Assignee: Kioxia Corporation
    Inventors: Masayuki Kitamura, Atsuko Sakata, Makoto Wada, Yuichi Yamazaki, Masayuki Katagiri, Akihiro Kajita, Tadashi Sakai, Naoshi Sakuma, Ichiro Mizushima
  • Patent number: 10580737
    Abstract: A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: March 3, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisao Miyazaki, Tadashi Sakai, Yasutaka Nishida, Takashi Yoshida, Yuichi Yamazaki, Masayuki Katagiri, Naoshi Sakuma
  • Publication number: 20190259707
    Abstract: A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisao MIYAZAKI, Tadashi Sakai, Yasutaka Nishida, Takashi Yoshida, Yuichi Yamazaki, Masayuki Katagiri, Naoshi Sakuma
  • Publication number: 20190259659
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki KITAMURA, Atsuko Sakata, Makoto Wada, Yuichi Yamazaki, Masayuki Katagiri, Akihiro Kajita, Tadashi Sakai, Naoshi Sakuma, Ichiro Mizushima
  • Patent number: 10325851
    Abstract: A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: June 18, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisao Miyazaki, Tadashi Sakai, Yasutaka Nishida, Takashi Yoshida, Yuichi Yamazaki, Masayuki Katagiri, Naoshi Sakuma
  • Patent number: 10325805
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: June 18, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Kitamura, Atsuko Sakata, Makoto Wada, Yuichi Yamazaki, Masayuki Katagiri, Akihiro Kajita, Tadashi Sakai, Naoshi Sakuma, Ichiro Mizushima
  • Publication number: 20190118852
    Abstract: There is a vehicle operation system (300) which includes a driving operating elements (302) that receive an operation of a driver for acceleration and deceleration or steering of a vehicle, and a control unit (301) that controls holding mechanisms (303) such that the driving operating elements are stored with a change in state of the holding mechanisms on the basis of an execution state of automated driving executed in a vehicle.
    Type: Application
    Filed: October 22, 2018
    Publication date: April 25, 2019
    Inventors: Takeyuki Suzuki, Yasutaka Innami, Yuichi Yamazaki, Masahide Kobayashi
  • Publication number: 20180277487
    Abstract: A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film.
    Type: Application
    Filed: August 30, 2017
    Publication date: September 27, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisao MIYAZAKI, Tadashi SAKAI, Yasutaka NISHIDA, Takashi YOSHIDA, Yuichi YAMAZAKI, Masayuki KATAGIRI, Naoshi SAKUMA
  • Patent number: 9997611
    Abstract: A graphene wiring structure of an embodiment has a multilayered graphene having a plurality of planar graphene sheets laminated, and a first interlayer substance being a metal oxyhalide between the plurality of planar graphene sheets.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: June 12, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisao Miyazaki, Tadashi Sakai, Masayuki Katagiri, Yuichi Yamazaki
  • Patent number: 9924593
    Abstract: A graphene wiring structure of an embodiment has a substrate, a metal part on the substrate, multilayered graphene connected to the metal part, a first insulative film on the substrate, and a second insulative film on the substrate. The metal part is present between the first insulative film and the second insulative film. Edges of the multilayered graphene are connected to the metal part. A side face of the first insulative film vertical to the substrate opposes a side face of the second insulative film vertical to the substrate. A first outer face of the multilayered graphene is in physical contact with a first side face of the first insulative film vertical to the substrate. A second outer face of the multilayered graphene is in physical contact with a second side face of the second insulative film vertical to the substrate.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: March 20, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Sakai, Yuichi Yamazaki, Hisao Miyazaki, Masayuki Katagiri, Taishi Ishikura, Akihiro Kajita
  • Patent number: 9893219
    Abstract: According to one embodiment, a graphene photodetector includes a substrate, a first insulating film, first and second high-refractive-index regions, first and second conductive semiconductor regions, a second insulating film, a graphene film, a third insulating film, third and fourth high-refractive-index regions, a fourth insulating film, first and second electrodes, and third and fourth electrodes. The first, second, third and fourth high-refractive-index regions and portions sandwiched by the first, second, third and fourth high-refractive-index regions constituting an integrated optical waveguide.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: February 13, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuo Suzuki, Yuichi Yamazaki
  • Publication number: 20180012846
    Abstract: A graphene structure of an embodiment includes multilayer graphene laminated with graphene sheets, and a first interlayer material being present between the graphene sheets of the multilayer graphene and containing a multimer of molybdenum oxide.
    Type: Application
    Filed: March 1, 2017
    Publication date: January 11, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisao MIYAZAKI, Takashi YOSHIDA, Masayuki KATAGIRI, Yuichi YAMAZAKI, Tadashi SAKAI
  • Publication number: 20170316973
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.
    Type: Application
    Filed: July 17, 2017
    Publication date: November 2, 2017
    Inventors: Masayuki KITAMURA, Atsuko SAKATA, Makoto WADA, Yuichi YAMAZAKI, Masayuki KATAGIRI, Akihiro KAJITA, Tadashi SAKAI, Naoshi SAKUMA, Ichiro MIZUSHIMA
  • Patent number: 9768372
    Abstract: A semiconductor device of an embodiment includes a layered substance formed by laminating two-dimensional substances in two or more layers. The layered substance includes at least either one of a p-type region having a first intercalation substance between layers of the layered substance and an n-type region having a second intercalation substance between layers of the layered substance. The layered substance includes a conductive region that is adjacent to at least either one of the p-type region and the n-type region. The conductive region includes neither the first intercalation substance nor the second intercalation substance. A sealing member is formed on the conductive region, or on the conductive region and an end of the layered substance.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: September 19, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisao Miyazaki, Yuichi Yamazaki, Tadashi Sakai