Patents by Inventor Yuichiro Ajima

Yuichiro Ajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200335143
    Abstract: A semiconductor memory apparatus includes a plurality of memory dies and a logic die, which are stacked to each other. The logic die includes a memory interface for a memory apparatus to be coupled to the semiconductor memory apparatus, and a switch coupled to a plurality of channels included in a control device which controls the semiconductor memory apparatus. The switch includes a first switch element which couples one of the plurality of channels to the memory interface or one of the plurality of memory dies, and a second switch element which couples another one of the plurality of channels to another one of the plurality of memory dies. Even if some memory dies are defective, the semiconductor memory apparatus is capable to operate.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 22, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Yuichiro Ajima, Toshiyuki SHIMIZU
  • Patent number: 10764409
    Abstract: A data communication device communicating with other devices via multiple communication paths includes a transmission unit and a reception unit. The transmission unit is configured to receive a packet containing header information and data, to output the header information to each of the communication paths, to divide the data into multiple data pieces, and to output the data pieces to the respective communication paths. The reception unit is configured to receive header information and a data piece for each of the communication paths, and to reconstruct a packet from the header information and the data piece received from each of the communication paths. In reconstructing the packet, the reception unit adjusts, for each of the communication paths, output timing of the data piece, based on the header information.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 1, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Jouji Kunii, Souta Kusachi, Yuichiro Ajima
  • Patent number: 10749634
    Abstract: A transmission device includes, a receiver that receives availability information of each of a plurality of first transmission paths, and a transmitter that divides data into a plurality of transmission blocks, groups the plurality of transmission blocks into a plurality of slices, each of the plurality of slices include a distinct subset of the plurality of transmission blocks, when the availability information indicates that each of the plurality of first transmission paths has an error occurrence below a threshold value, transmits a different one of the plurality of slices to each of the plurality of first transmission paths.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: August 18, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Souta Kusachi, Jouji Kunii, Yuichiro Ajima
  • Publication number: 20200249593
    Abstract: According to one embodiment, an image forming apparatus includes a developing device, a sensor, a control information obtaining unit, and a control unit. The developing device forms an image on an image carrier using a developer. The sensor generates a signal indicating a measurement value related to the developer. The control information obtaining unit obtains, as control information of the developing device, one or more pieces of the control information pre-associated with the measurement value, from a recording medium associated with the developer. The control unit selects the control information associated with the measurement value indicated by the signal, from the one or more pieces of control information obtained from the recording medium. The control unit controls an operation of the developing device based on the selected control information.
    Type: Application
    Filed: August 19, 2019
    Publication date: August 6, 2020
    Applicant: TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Hisanobu AJIMA, Nobuo TOHATA, Yuichiro TAKEDA
  • Patent number: 10609188
    Abstract: An information processing apparatus includes a receiver to receive data-packets, the data-packets generated by dividing a message into division-data and storing, for each of the division-data, one of the plurality of division data into one of the plurality of data packets, wherein each of the data-packets also includes a data value indicating a quantity of the division-data and data indicating whether or not the data-packet includes final division data corresponding to an end of the message, a memory, and a processor to store the division-data that is contained in a packet of the data-packets that are received, in the memory, and suppress the final division-data from being stored in the memory until the quantity of the data-packets received by the receiver equates to the data value indicating the quantity of the division-data, in a case where the final division-data is received earlier than any one of the other division-data.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: March 31, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Shinya Hiramoto, Yuji Kondo, Yuichiro Ajima
  • Patent number: 10592299
    Abstract: A computation node device includes a buffer configured to store first data, a receiver configured to receive a packet including second data, an error check circuit configured to perform an error check of the packet and output a check result, and an operation device configured to perform, before receiving the check result output from the error check circuit, a reduction operation by using the first data stored in the buffer and the second data included in the packet and output an operation result of the reduction operation when the check result output from the error check circuit indicates non-existence of an error in the packet.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: March 17, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Yuji Kondo, Shinya Hiramoto, Yuichiro Ajima
  • Publication number: 20190334836
    Abstract: An information processing apparatus includes a plurality of processors and a plurality of links provided between the processors in a plurality of axis directions. Each of the processors includes a processor circuit, a memory, a memory controller, and an interconnect coupled to the processor circuit. The interconnect includes: a network switch configured to perform switching between the first links and a second link to its own processor; link counters provided to input links and output links of the first links and the second link respectively, the link counters being configured to count at least the number of packets passing through the input links and the output links; and a recorder configured to store count values of the link counters in the memory via the memory controller without a control by the processor circuit.
    Type: Application
    Filed: April 18, 2019
    Publication date: October 31, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Yuichiro Ajima, Shinya Hiramoto, YUJI KONDO
  • Publication number: 20190324927
    Abstract: A processor includes: a plurality of processor cores; an interconnector including a reduction operation device and configured to communicate with another processor; a memory controller configured to control a main memory; a bus configured to couple the plurality of processor cores, the interconnector, and the memory controller to each other; and a reduction operation buffer coupled to the bus and the interconnector, wherein each of the processor cores writes control information to control the reduction operation device included in the interconnector and a value to be operated by the reduction operation device in the reduction operation buffer, and the interconnector reads out the control information and the value from the reduction operation buffer and delivers the control information and the value to the reduction operation device.
    Type: Application
    Filed: March 21, 2019
    Publication date: October 24, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Yuichiro Ajima, Shinya Hiramoto, YUJI KONDO
  • Patent number: 10430375
    Abstract: A parallel computing system includes a plurality of processors multi-dimensionally commented by an interconnection network, wherein each of the processors in the parallel computing system determines, in dimensional order, communication channels to other processors in the interconnection network, each of the processors sets, as relative coordinates of destination processors with respect to the plurality of processors in data communications performed at a same timing, relative coordinates common to all of the processors, and each of the processors performs data communications with destination processors having the set relative coordinates.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: October 1, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Yuichiro Ajima, Toshiyuki Shimizu, Hiroaki Ishihata
  • Publication number: 20190235947
    Abstract: A transfer apparatus for performing transmission and reception of data using a plurality of lanes includes: a transmission control unit configured to, upon receiving a transmission instruction for performing a data transfer in a redundant mode in which the same data is transferred using a plurality of lanes, output transmission data as first data and second data without renegotiation with another transfer apparatus; a first transmission unit configured to transmit the first data output by the transmission control unit via a first lane; and a second transmission unit configured to transmit the second data output by the transmission control unit via a second lane.
    Type: Application
    Filed: January 2, 2019
    Publication date: August 1, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Yuichiro Ajima, Jouji KUNII, Souta Kusachi
  • Patent number: 10353857
    Abstract: A packet transmitting unit transmits, to a node via RDMA communication, a packet with a first identifier that represents a predetermined process and a second identifier that represents a destination communication interface and is a logical identifier, as a destination, being added thereto. A plurality of communication interfaces exist. A packet receiving unit receives a packet transmitted from the node via RDMA communication, selects a communication interface that is a destination of a received packet and is used in the predetermined process, based on the first identifier and the second identifier added to the received packet, and transfers the received packet to a selected communication interface.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: July 16, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Yuichiro Ajima
  • Patent number: 10230625
    Abstract: An information processing apparatus including: an arithmetic processing unit; and a communication device configured to receive data from another information processing apparatus through a plurality of first lanes and to output the received data to the arithmetic processing unit, wherein the communication device includes a detection unit that detects a failure of the plurality of first lanes; and a control unit that performs a first degradation process of stopping use of any one of the plurality of first lanes, based on a degradation request, performs a restoration process of resuming use of a first lane for which use has been stopped, based on a restoration request, and performs a second degradation process of stopping use of a first lane for which use has been resumed, when the detection unit detects a failure of the first lane for which use has been resumed, in the restoration process.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: March 12, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Masahiro Maeda, Koichiro Takayama, Tomohiro Inoue, Shinya Hiramoto, Shun Ando, Yuichiro Ajima
  • Publication number: 20190075191
    Abstract: A data communication device communicating with other devices via multiple communication paths includes a transmission unit and a reception unit. The transmission unit is configured to receive a packet containing header information and data, to output the header information to each of the communication paths, to divide the data into multiple data pieces, and to output the data pieces to the respective communication paths. The reception unit is configured to receive header information and a data piece for each of the communication paths, and to reconstruct a packet from the header information and the data piece received from each of the communication paths. In reconstructing the packet, the reception unit adjusts, for each of the communication paths, output timing of the data piece, based on the header information.
    Type: Application
    Filed: August 21, 2018
    Publication date: March 7, 2019
    Inventors: Jouji KUNII, Souta KUSACHI, Yuichiro AJIMA
  • Publication number: 20190073247
    Abstract: A computation node device includes a buffer configured to store first data, a receiver configured to receive a packet including second data, an error check circuit configured to perform an error check of the packet and output a check result, and an operation device configured to perform, before receiving the check result output from the error check circuit, a reduction operation by using the first data stored in the buffer and the second data included in the packet and output an operation result of the reduction operation when the check result output from the error check circuit indicates non-existence of an error in the packet.
    Type: Application
    Filed: August 6, 2018
    Publication date: March 7, 2019
    Applicant: FUJITSU LIMITED
    Inventors: YUJI KONDO, Shinya Hiramoto, Yuichiro Ajima
  • Publication number: 20190068329
    Abstract: A transmission device includes, a receiver that receives availability information of each of a plurality of first transmission paths, and a transmitter that divides data into a plurality of transmission blocks, groups the plurality of transmission blocks into a plurality of slices, each of the plurality of slices include a distinct subset of the plurality of transmission blocks, when the availability information indicates that each of the plurality of first transmission paths has an error occurrence below a threshold value, transmits a different one of the plurality of slices to each of the plurality of first transmission paths.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 28, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Souta Kusachi, Jouji KUNII, Yuichiro Ajima
  • Publication number: 20180309859
    Abstract: An information processing apparatus includes a receiver to receive data-packets, the data-packets generated by dividing a message into division-data and storing, for each of the division-data, one of the plurality of division data into one of the plurality of data packets, wherein each of the data-packets also includes a data value indicating a quantity of the division-data and data indicating whether or not the data-packet includes final division data corresponding to an end of the message, a memory, and a processor to store the division-data that is contained in a packet of the data-packets that are received, in the memory, and suppress the final division-data from being stored in the memory until the quantity of the data-packets received by the receiver equates to the data value indicating the quantity of the division-data, in a case where the final division-data is received earlier than any one of the other division-data.
    Type: Application
    Filed: April 3, 2018
    Publication date: October 25, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Shinya Hiramoto, YUJI KONDO, Yuichiro Ajima
  • Patent number: 10002078
    Abstract: An information processing apparatus includes: storage devices that store data; a data generation unit that generates padding-added data by adding padding to the data, based on adjustment information included in received data; and a storage processing unit that stores the padding-added data generated by the data generation unit in the storage devices. It is possible to shorten a latency even when non-aligned data is received.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: June 19, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Shinya Hiramoto, Yuichiro Ajima, Tomohiro Inoue, Yuta Toyoda, Shun Ando, Masahiro Maeda
  • Publication number: 20170293589
    Abstract: A packet transmitting unit transmits, to a node via RDMA communication, a packet with a first identifier that represents a predetermined process and a second identifier that represents a destination communication interface and is a logical identifier, as a destination, being added thereto. A plurality of communication interfaces exist. A packet receiving unit receives a packet transmitted from the node via RDMA communication, selects a communication interface that is a destination of a received packet and is used in the predetermined process, based on the first identifier and the second identifier added to the received packet, and transfers the received packet to a selected communication interface.
    Type: Application
    Filed: March 27, 2017
    Publication date: October 12, 2017
    Applicant: FUJITSU LIMITED
    Inventor: Yuichiro Ajima
  • Publication number: 20170295237
    Abstract: A parallel processing apparatus includes first, second, and third nodes. The first node includes a processor that starts RDMA communication of certain data and receives a response of the RDMA communication, and a first communication interface that transmits an RDMA communication request giving instructions to transmit the certain data by RDMA when the processor starts the RDMA communication of the certain data. The second node includes a memory that stores therein the certain data, and a second communication interface that receives the RDMA communication request transmitted from the first communication interface and transmits the certain data stored in the memory to the third node by RDMA. The third node includes a memory, and a third communication interface that receives the certain data transmitted from the second communication interface by RDMA, stores the certain data in the memory, and generates and transmits the response of the RDMA communication.
    Type: Application
    Filed: March 15, 2017
    Publication date: October 12, 2017
    Applicant: FUJITSU LIMITED
    Inventor: Yuichiro Ajima
  • Patent number: 9749222
    Abstract: A parallel computer includes a plurality of nodes. Each of the nodes includes a router directly or indirectly connected to each of the other nodes and a network interface connected to an external network of the parallel computer. The network interface includes a storage unit that holds detour route information indicating a detour route corresponding to a communication route from a node in which the network interface is included to another node. The network interface further includes a reception processing unit that, when the network interface receives data destined to one node of the parallel computer from the external network, sets detour route information corresponding to a communication route from the node in which the network interface is included to the destination node of the data for the data and transmits the data for which the detour route information is set to the destination node.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: August 29, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Tomohiro Inoue, Yuichiro Ajima, Shinya Hiramoto, Masahiro Maeda, Shun Ando, Yuta Toyoda