Abstract: A semiconductor memory apparatus includes a plurality of memory dies and a logic die, which are stacked to each other. The logic die includes a memory interface for a memory apparatus to be coupled to the semiconductor memory apparatus, and a switch coupled to a plurality of channels included in a control device which controls the semiconductor memory apparatus. The switch includes a first switch element which couples one of the plurality of channels to the memory interface or one of the plurality of memory dies, and a second switch element which couples another one of the plurality of channels to another one of the plurality of memory dies. Even if some memory dies are defective, the semiconductor memory apparatus is capable to operate.

Abstract: A transfer apparatus for performing transmission and reception of data using a plurality of lanes includes: a transmission control unit configured to, upon receiving a transmission instruction for performing a data transfer in a redundant mode in which the same data is transferred using a plurality of lanes, output transmission data as first data and second data without renegotiation with another transfer apparatus; a first transmission unit configured to transmit the first data output by the transmission control unit via a first lane; and a second transmission unit configured to transmit the second data output by the transmission control unit via a second lane.

Abstract: A processor includes: a plurality of processor cores; an interconnector including a reduction operation device and configured to communicate with another processor; a memory controller configured to control a main memory; a bus configured to couple the plurality of processor cores, the interconnector, and the memory controller to each other; and a reduction operation buffer coupled to the bus and the interconnector, wherein each of the processor cores writes control information to control the reduction operation device included in the interconnector and a value to be operated by the reduction operation device in the reduction operation buffer, and the interconnector reads out the control information and the value from the reduction operation buffer and delivers the control information and the value to the reduction operation device.

Abstract: An information processing apparatus includes a plurality of processors and a plurality of links provided between the processors in a plurality of axis directions. Each of the processors includes a processor circuit, a memory, a memory controller, and an interconnect coupled to the processor circuit. The interconnect includes: a network switch configured to perform switching between the first links and a second link to its own processor; link counters provided to input links and output links of the first links and the second link respectively, the link counters being configured to count at least the number of packets passing through the input links and the output links; and a recorder configured to store count values of the link counters in the memory via the memory controller without a control by the processor circuit.

Abstract: A semiconductor memory apparatus includes a plurality of memory dies and a logic die, which are stacked to each other. The logic die includes a memory interface for a memory apparatus to be coupled to the semiconductor memory apparatus, and a switch coupled to a plurality of channels included in a control device which controls the semiconductor memory apparatus. The switch includes a first switch element which couples one of the plurality of channels to the memory interface or one of the plurality of memory dies, and a second switch element which couples another one of the plurality of channels to another one of the plurality of memory dies. Even if some memory dies are defective, the semiconductor memory apparatus is capable to operate.

Abstract: A data communication device communicating with other devices via multiple communication paths includes a transmission unit and a reception unit. The transmission unit is configured to receive a packet containing header information and data, to output the header information to each of the communication paths, to divide the data into multiple data pieces, and to output the data pieces to the respective communication paths. The reception unit is configured to receive header information and a data piece for each of the communication paths, and to reconstruct a packet from the header information and the data piece received from each of the communication paths. In reconstructing the packet, the reception unit adjusts, for each of the communication paths, output timing of the data piece, based on the header information.

Abstract: A transmission device includes, a receiver that receives availability information of each of a plurality of first transmission paths, and a transmitter that divides data into a plurality of transmission blocks, groups the plurality of transmission blocks into a plurality of slices, each of the plurality of slices include a distinct subset of the plurality of transmission blocks, when the availability information indicates that each of the plurality of first transmission paths has an error occurrence below a threshold value, transmits a different one of the plurality of slices to each of the plurality of first transmission paths.

Abstract: An information processing apparatus includes a receiver to receive data-packets, the data-packets generated by dividing a message into division-data and storing, for each of the division-data, one of the plurality of division data into one of the plurality of data packets, wherein each of the data-packets also includes a data value indicating a quantity of the division-data and data indicating whether or not the data-packet includes final division data corresponding to an end of the message, a memory, and a processor to store the division-data that is contained in a packet of the data-packets that are received, in the memory, and suppress the final division-data from being stored in the memory until the quantity of the data-packets received by the receiver equates to the data value indicating the quantity of the division-data, in a case where the final division-data is received earlier than any one of the other division-data.

Abstract: A computation node device includes a buffer configured to store first data, a receiver configured to receive a packet including second data, an error check circuit configured to perform an error check of the packet and output a check result, and an operation device configured to perform, before receiving the check result output from the error check circuit, a reduction operation by using the first data stored in the buffer and the second data included in the packet and output an operation result of the reduction operation when the check result output from the error check circuit indicates non-existence of an error in the packet.

Abstract: An information processing apparatus includes a plurality of processors and a plurality of links provided between the processors in a plurality of axis directions. Each of the processors includes a processor circuit, a memory, a memory controller, and an interconnect coupled to the processor circuit. The interconnect includes: a network switch configured to perform switching between the first links and a second link to its own processor; link counters provided to input links and output links of the first links and the second link respectively, the link counters being configured to count at least the number of packets passing through the input links and the output links; and a recorder configured to store count values of the link counters in the memory via the memory controller without a control by the processor circuit.

Abstract: A processor includes: a plurality of processor cores; an interconnector including a reduction operation device and configured to communicate with another processor; a memory controller configured to control a main memory; a bus configured to couple the plurality of processor cores, the interconnector, and the memory controller to each other; and a reduction operation buffer coupled to the bus and the interconnector, wherein each of the processor cores writes control information to control the reduction operation device included in the interconnector and a value to be operated by the reduction operation device in the reduction operation buffer, and the interconnector reads out the control information and the value from the reduction operation buffer and delivers the control information and the value to the reduction operation device.

Abstract: A parallel computing system includes a plurality of processors multi-dimensionally commented by an interconnection network, wherein each of the processors in the parallel computing system determines, in dimensional order, communication channels to other processors in the interconnection network, each of the processors sets, as relative coordinates of destination processors with respect to the plurality of processors in data communications performed at a same timing, relative coordinates common to all of the processors, and each of the processors performs data communications with destination processors having the set relative coordinates.

Abstract: A transfer apparatus for performing transmission and reception of data using a plurality of lanes includes: a transmission control unit configured to, upon receiving a transmission instruction for performing a data transfer in a redundant mode in which the same data is transferred using a plurality of lanes, output transmission data as first data and second data without renegotiation with another transfer apparatus; a first transmission unit configured to transmit the first data output by the transmission control unit via a first lane; and a second transmission unit configured to transmit the second data output by the transmission control unit via a second lane.

Abstract: A packet transmitting unit transmits, to a node via RDMA communication, a packet with a first identifier that represents a predetermined process and a second identifier that represents a destination communication interface and is a logical identifier, as a destination, being added thereto. A plurality of communication interfaces exist. A packet receiving unit receives a packet transmitted from the node via RDMA communication, selects a communication interface that is a destination of a received packet and is used in the predetermined process, based on the first identifier and the second identifier added to the received packet, and transfers the received packet to a selected communication interface.

Abstract: An information processing apparatus including: an arithmetic processing unit; and a communication device configured to receive data from another information processing apparatus through a plurality of first lanes and to output the received data to the arithmetic processing unit, wherein the communication device includes a detection unit that detects a failure of the plurality of first lanes; and a control unit that performs a first degradation process of stopping use of any one of the plurality of first lanes, based on a degradation request, performs a restoration process of resuming use of a first lane for which use has been stopped, based on a restoration request, and performs a second degradation process of stopping use of a first lane for which use has been resumed, when the detection unit detects a failure of the first lane for which use has been resumed, in the restoration process.

Abstract: A computation node device includes a buffer configured to store first data, a receiver configured to receive a packet including second data, an error check circuit configured to perform an error check of the packet and output a check result, and an operation device configured to perform, before receiving the check result output from the error check circuit, a reduction operation by using the first data stored in the buffer and the second data included in the packet and output an operation result of the reduction operation when the check result output from the error check circuit indicates non-existence of an error in the packet.

Abstract: A data communication device communicating with other devices via multiple communication paths includes a transmission unit and a reception unit. The transmission unit is configured to receive a packet containing header information and data, to output the header information to each of the communication paths, to divide the data into multiple data pieces, and to output the data pieces to the respective communication paths. The reception unit is configured to receive header information and a data piece for each of the communication paths, and to reconstruct a packet from the header information and the data piece received from each of the communication paths. In reconstructing the packet, the reception unit adjusts, for each of the communication paths, output timing of the data piece, based on the header information.

Abstract: A transmission device includes, a receiver that receives availability information of each of a plurality of first transmission paths, and a transmitter that divides data into a plurality of transmission blocks, groups the plurality of transmission blocks into a plurality of slices, each of the plurality of slices include a distinct subset of the plurality of transmission blocks, when the availability information indicates that each of the plurality of first transmission paths has an error occurrence below a threshold value, transmits a different one of the plurality of slices to each of the plurality of first transmission paths.

Abstract: An information processing apparatus includes a receiver to receive data-packets, the data-packets generated by dividing a message into division-data and storing, for each of the division-data, one of the plurality of division data into one of the plurality of data packets, wherein each of the data-packets also includes a data value indicating a quantity of the division-data and data indicating whether or not the data-packet includes final division data corresponding to an end of the message, a memory, and a processor to store the division-data that is contained in a packet of the data-packets that are received, in the memory, and suppress the final division-data from being stored in the memory until the quantity of the data-packets received by the receiver equates to the data value indicating the quantity of the division-data, in a case where the final division-data is received earlier than any one of the other division-data.

Abstract: An information processing apparatus includes: storage devices that store data; a data generation unit that generates padding-added data by adding padding to the data, based on adjustment information included in received data; and a storage processing unit that stores the padding-added data generated by the data generation unit in the storage devices. It is possible to shorten a latency even when non-aligned data is received.