Patents by Inventor Yuichiro Ishii

Yuichiro Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10706902
    Abstract: A semiconductor device includes: memory cells, first word lined arranged for first ports and each arranging corresponding to respective rows of the memory cells; second word lines arranged for second ports and each arranged corresponding to respective rows of the memory cells, first dummy word lines each provided above the respective first word lines, second dummy word lines each provided above the respective second word lines, a word line driver driving the first and second word lines, and a dummy word line driver driving, in an opposite phase, the second dummy word line for the adjacent second word line according to driving of the first word line from among the first and second word lines, or the first dummy word line for the adjacent first word line according to driving of the second word line from among the first and second word lines.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuichiro Ishii
  • Patent number: 10706917
    Abstract: Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Yuichiro Ishii, Yohei Sawada, Makoto Yabuuchi
  • Publication number: 20200202968
    Abstract: A semiconductor device has a memory circuit and a logic circuit coupled with a memory circuit. the memory circuit included a memory array in which memory cells are arranged in a matrix, an input/output circuit for writing data to the memory cells and reading data from the memory cells, and a control circuit for generating a control signal for controlling the input/output circuit. In a test operation for testing the logic circuit, the input/output circuit receives a test data. The control circuit raises and lowers the control signal based on a rising and a falling of an external clock signal, thereby the test data is output to the logic circuit via the input/output circuit.
    Type: Application
    Filed: November 13, 2019
    Publication date: June 25, 2020
    Inventor: Yuichiro ISHII
  • Patent number: 10658028
    Abstract: A semiconductor storage device includes a plurality of memory cells arranged in a matrix, a word line provided corresponding to a memory cell row, a dummy word line formed in a metal interconnection layer adjacent to a metal interconnection layer in which the word line is formed, a word driver circuit configured to drive the word line, and a dummy word driver circuit configured to increase voltage on the word line based on interline capacitance between the word line and the dummy word line.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: May 19, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichiro Ishii, Shinji Tanaka
  • Patent number: 10515672
    Abstract: A semiconductor memory device including a pair of first bit lines extended in a first direction, a pair of second bit lines extended in the first direction, a first word line extended in a second direction crossing the first direction, a second word line extended in the second direction, a memory cell surrounded by the first bit line, the second bit line, the first word line, and the second word line, and including a drive transistor, a first transfer transistor coupled with one of the pair of first bit lines, and having a gate coupled with the first word line, a second transfer transistor coupled with one of the pair of second bit lines, and having a gate coupled with the second word line, and a load transistor, a write drive circuit that transfers data to the memory cell.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 24, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinji Tanaka, Yuichiro Ishii, Masaki Tsukude, Yoshikazu Saito
  • Patent number: 10482949
    Abstract: A semiconductor device includes a first mode and a second mode different from the first mode, includes a memory circuit including a first switch, a memory array, and a peripheral circuit. A first power source line is electrically coupled with an I/O circuit of the peripheral circuit and is supplied with a first voltage in the first mode. A second power source line is electrically coupled with a memory cell of the memory array, and supplied with a second voltage lower than the first voltage in the second mode.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: November 19, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichiro Ishii, Atsushi Miyanishi, Kazumasa Yanagisawa
  • Patent number: 10460795
    Abstract: A semiconductor device includes a latch circuit receiving a first signal, generated in synchronization with a clock signal, from a pulse generation circuit, and generating a second signal; a first delay circuit receiving the second signal from the latch circuit, and generating a third signal by delaying the second signal; a second delay circuit receiving the third signal from the first delay circuit, and generating a fourth signal by delaying the third signal; and a logic circuit receiving the second and fourth signals from the latch and second delay circuits, respectively, and generating a word line control signal based on one of the second signal and the fourth signal. The latch circuit generates the second signal of a first level based on the first signal, and generates the second signal of a second level, which is different from the first level, based on the third signal.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: October 29, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichiro Ishii, Makoto Yabuuchi, Masao Morimoto
  • Patent number: 10453519
    Abstract: A semiconductor device includes a SRAM (Static Random Access Memory) circuit. The SRAM circuit includes a static memory cell, a word line coupled with the static memory cell, a pair of bit lines coupled with the static memory cell, a first interconnection coupled with the static memory cell, and supplying a first potential, a second interconnection coupled with the static memory cell, and supplying a second potential lower than the first potential, a first potential control circuit controlling a potential of the second interconnection, and a second potential control circuit controlling a potential of the first interconnection. The SRAM circuit includes, as an operation mode a first operation mode for reading data from the SRAM circuit, or for writing data into the SRAM circuit, and a second operation mode for reducing power consumption than the first operation mode.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: October 22, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yohei Sawada, Makoto Yabuuchi, Yuichiro Ishii
  • Patent number: 10453520
    Abstract: A memory circuit includes: a control circuit generating first and second start signals within a single signal cycle of an input clock signal; an address control circuit coupled to a plurality of address ports for receiving a plurality of address signals and activating one of word lines corresponding to one of the address signals based on the first or second start signals; and a data input/output circuit for writing or reading data by selecting one of memory cells coupled to the activated word line. The control circuit includes: a start signal generation unit that generates the first start signal in response to a first pulse signal and the second start signal in response to a second pulse signal, and a pulse signal generation unit that generates the first pulse signal in response to the input clock signal and the second signal in response to the first start signal.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: October 22, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuichiro Ishii
  • Patent number: 10381056
    Abstract: A dual port static random access memory (DPSRAM) cell includes a first power line, a first bit line and a second bit line. The first power line is disposed between a first word line and a second word line. The first bit line is disposed between the first word line and the first power line. The second bit line is disposed between the second word line and the first power line.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: August 13, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tien-Yu Lu, Chun-Hsien Huang, Ching-Cheng Lung, Yu-Tse Kuo, Shou-Sian Chen, Koji Nii, Yuichiro Ishii
  • Patent number: 10373675
    Abstract: A semiconductor storage device includes, a memory array, a plurality of memory cells provided in rows and columns, and a control circuit for controlling the memory array, each of the memory cells being a static-type memory cell comprising driving transistors, transfer transistors, and load elements.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: August 6, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshisato Yokoyama, Yuichiro Ishii
  • Patent number: 10360091
    Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: July 23, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichiro Ishii, Atsushi Miyanishi, Yoshikazu Saito
  • Patent number: 10354722
    Abstract: An assist driver is coupled to an end of a word line to which a word line driver is not coupled, and couples the other end of the word line to a first power source, in accordance with a voltage of the other end of the word line.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 16, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Yuichiro Ishii
  • Publication number: 20190206459
    Abstract: A dual port static random access memory (DPSRAM) cell includes a first power line, a first bit line and a second bit line. The first power line is disposed between a first word line and a second word line. The first bit line is disposed between the first word line and the first power line. The second bit line is disposed between the second word line and the first power line.
    Type: Application
    Filed: May 29, 2018
    Publication date: July 4, 2019
    Inventors: Tien-Yu Lu, Chun-Hsien Huang, Ching-Cheng Lung, Yu-Tse Kuo, Shou-Sian Chen, Koji Nii, Yuichiro Ishii
  • Publication number: 20190198074
    Abstract: A semiconductor device includes: memory cells, first word lined arranged for first ports and each arranging corresponding to respective rows of the memory cells; second word lines arranged for second ports and each arranged corresponding to respective rows of the memory cells, first dummy word lines each provided above the respective first word lines, second dummy word lines each provided above the respective second word lines, a word line driver driving the first and second word lines, and a dummy word line driver driving, in an opposite phase, the second dummy word line for the adjacent second word line according to driving of the first word line from among the first and second word lines, or the first dummy word line for the adjacent first word line according to driving of the second word line from among the first and second word lines.
    Type: Application
    Filed: November 15, 2018
    Publication date: June 27, 2019
    Inventor: Yuichiro ISHII
  • Publication number: 20190198499
    Abstract: A semiconductor device includes a semiconductor substrate, a first well region formed on the semiconductor substrate, a first fin integrally formed of the semiconductor substrate on the first well region and extended in a first direction in a plan view, a first electrode formed on the first fin via a first gate insulating film, and extended in a second direction crossing the first direction in the plan view, a tap region formed on the semiconductor substrate adjacent to the first well region in the second direction, and supplying a first potential to the first well region, a second fin integrally formed of the semiconductor substrate on the tap region and extended in the first direction in the plan view, and a first wiring layer formed on the second fin in a portion overlapping the tap region in the plan view.
    Type: Application
    Filed: February 27, 2019
    Publication date: June 27, 2019
    Inventors: Makoto YABUUCHI, Yuichiro Ishii
  • Publication number: 20190189197
    Abstract: Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.
    Type: Application
    Filed: October 31, 2018
    Publication date: June 20, 2019
    Inventors: Koji NII, Yuichiro ISHII, Yohei SAWADA, Makoto YABUUCHI
  • Patent number: 10325650
    Abstract: A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 18, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuichiro Ishii
  • Publication number: 20190172524
    Abstract: A semiconductor device includes a first mode and a second mode different from the first mode, includes a memory circuit including a first switch, a memory array, and a peripheral circuit. A first power source line is electrically coupled with an I/O circuit of the peripheral circuit and is supplied with a first voltage in the first mode. A second power source line is electrically coupled with a memory cell of the memory array, and supplied with a second voltage lower than the first voltage in the second mode.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 6, 2019
    Inventors: Yuichiro ISHII, Atsushi MIYANISHI, Kazumasa YANAGISAWA
  • Publication number: 20190122703
    Abstract: A semiconductor memory device including a pair of first bit lines extended in a first direction, a pair of second bit lines extended in the first direction, a first word line extended in a second direction crossing the first direction, a second word line extended in the second direction, a memory cell surrounded by the first bit line, the second bit line, the first word line, and the second word line, and including a drive transistor, a first transfer transistor coupled with one of the pair of first bit lines, and having a gate coupled with the first word line, a second transfer transistor coupled with one of the pair of second bit lines, and having a gate coupled with the second word line, and a load transistor, a write drive circuit that transfers data to the memory cell.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 25, 2019
    Inventors: Shinji Tanaka, Yuichiro Ishii, Masaki Tsukude, Yoshikazu Saito