Abstract: A processing agent containing five specified kinds of components including esters and ethers as required components is used in the production or fabrication process of synthetic fibers such that superior spinning property is maintained and synthetic fibers with superior yarn quality and dyeing property can be obtained. Aqueous liquids of such processing agents, processing methods using such liquids and synthetic fibers obtained by such methods are also presented.

Abstract: A processing agent containing five specified kinds of components including esters and ethers as required components is used in the production or fabrication process of synthetic fibers such that superior spinning property is maintained and synthetic fibers with superior yarn quality and dyeing property can be obtained. Aqueous liquids of such processing agents, processing methods using such liquids and synthetic fibers obtained by such methods are also presented.

Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn?1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn?1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn?1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn?1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

Abstract: The present invention provides a surface-coated article possessing a high hardness coating that has a Vickers hardness that is equal to or greater than that of conventional high hardness coatings, and which has an oxidation initiation temperature, which is an expression of resistance to oxidation, that is higher than that of conventional high hardness coatings. A coating layer containing a compound nitride that employs as main components Al and at least one element selected from the group consisting of Zr, Hf, Pd, Ir and the rare earth elements is formed on or over a base material.

Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn?1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn?1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn?1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn?1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn?1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn?1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

Abstract: A brake hose has an inner rubber layer, an outer rubber layer, and at least two reinforcing layers provided between the inner rubber layer and the outer rubber layer. The reinforcing layers include an upper yarn layer, and a lower yarn layer. Polyester yarn having a tensile strength of not lower than 6.9 g per unit dtex and having a stretchability of 2.6±1.0% at 2.7 g load per unit dtex is used as lower yarn in the lower yarn layer. The braid angle of the lower yarn layer with respect to the axial direction of the hose is set at 59±2°.

Abstract: A brake hose has an inner rubber layer, an outer rubber layer, and at least two reinforcing layers provided between the inner rubber layer and the outer rubber layer. The reinforcing layers include an upper yarn layer, and a lower yarn layer. Polyester yarn having a tensile strength of not lower than 6.9 g per unit dtex and having a stretchability of 2.6±1.0% at 2.7 g load per unit dtex is used as lower yarn in the lower yarn layer.

Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

Abstract: In a crystal structure analysis using an X-ray diffraction method or the like, using a measured value y.sup.0 i of a sample and an expected crystal structure parameter, a vector F having the logarithmic conversion value of the measured value as a matrix element is determined by f.sub.i =k.multidot.log(y.sub.i +.delta.-b.sub.i) from a value y.sub.i of the measured value y.sup.0 i after count missing correction of a detector, a background strength b.sub.i and a positive value .delta. of less than 1, a vector F.sub.c having the logarithmic conversion value of the calculated value as a matrix element is obtained by F.sub.ci =k.multidot.log(y.sub.ci) from the value vector obtained by calculation from the crystal structure parameter, a weight matrix W is obtained from device function matrix, systematic error, and accidental error, and the calculated value vector F.sub.c is determined so that a residual square sum s (=(F-F.sub.c).sup.t W(F-F.sub.c)) obtained by multiplying a difference between F and F.sub.