Patents by Inventor Yuichiro Takashina

Yuichiro Takashina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Display device and manufacturing method therefor
    Patent number: 7952095
    Abstract: In a display device of the present invention which forms thin film transistors on a substrate, the thin film transistor comprises: a silicon nitride film which is formed on the substrate in a state that the silicon nitride film covers a gate electrode; a silicon oxide film which is selectively formed on the silicon nitride film; a semiconductor layer which is formed at least on an upper surface of the silicon oxide film and includes a pseudo single crystal layer or a polycrystalline layer; and a drain electrode and a source electrode which are formed on an upper surface of the semiconductor layer by way of a contact layer, wherein either one of the pseudo single crystal layer and the poly-crystalline layer is formed by crystallizing the amorphous silicon layer, and a peripheral-side wall surface of the pseudo single crystal layer or the polycrystalline layer is contiguously constituted with a peripheral-side wall surface of the silicon oxide film below the pseudo single crystal layer or the polycrystalline la
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: May 31, 2011
    Assignee: Hitachi Displays, Ltd.
    Inventors: Eiji Oue, Takuo Kaitoh, Hidekazu Miyake, Toshio Miyazawa, Yuichiro Takashina
  • Display Device and Manufacturing Method Therefor
    Publication number: 20090065777
    Abstract: In a display device of the present invention which forms thin film transistors on a substrate, the thin film transistor comprises: a silicon nitride film which is formed on the substrate in a state that the silicon nitride film covers a gate electrode; a silicon oxide film which is selectively formed on the silicon nitride film; a semiconductor layer which is formed at least on an upper surface of the silicon oxide film and includes a pseudo single crystal layer or a polycrystalline layer; and a drain electrode and a source electrode which are formed on an upper surface of the semiconductor layer by way of a contact layer, wherein either one of the pseudo single crystal layer and the poly-crystalline layer is formed by crystallizing the amorphous silicon layer, and a peripheral-side wall surface of the pseudo single crystal layer or the polycrystalline layer is contiguously constituted with a peripheral-side wall surface of the silicon oxide film below the pseudo single crystal layer or the polycrystalline la
    Type: Application
    Filed: September 11, 2008
    Publication date: March 12, 2009
    Inventors: Eiji Oue, Takuo Kaitoh, Hidekazu Miyake, Toshio Miyazawa, Yuichiro Takashina