Patents by Inventor Yuichiro Yamada

Yuichiro Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6875631
    Abstract: A CF card (1) comprises: a casing constituted by two panel plates (2, 2) and a frame (3); and a printed wiring board (4) accommodated in the casing. A plurality of claw-like engaging parts (5) are provided to the peripheries of the panel plates (2). When the CF card (1) is assembled, the engaging parts (5) of the first panel plate (2) are inserted into through holes of a long groove (8) provided in the frame (3) and then the printed wiring board (4) is mounted on the panel plate (2) located at the inside of the frame (3). Thereafter, the engaging parts (5) of the second panel plate (2) are inserted into the through holes of the long groove (8) from the surface located in the opposite side of the frame (3). There are two types of engaging parts (5): one having lances and the other having holes. Inside the through holes, the lances of the engaging parts (5) of one panel plate (2) are inserted into the holes of the engaging parts (5) of the other panel plate (2).
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: April 5, 2005
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Sanwa Denki Kogyo Co., Ltd.
    Inventors: Hirotaka Nishizawa, Hideki Tanaka, Yuichiro Yamada, Tomoaki Kudaishi, Akira Katsumata
  • Patent number: 6861735
    Abstract: A resin molded type semiconductor device has: a semiconductor chip (12) which is mounted on a die pad portion (11) of a lead frame (9); thin metal wires (14) which connect terminals of the semiconductor chip (12) to inner lead portions (13) of the lead frame (9); and a sealing resin (15), and the lead frame (9) is subjected to an upsetting process so that a supporting portion (11) is located at a position higher than the inner lead portions (13). Since the sealing resin of a thickness corresponding to the step difference of the upsetting exists below the supporting portion, the adhesiveness between the lead frame and the sealing resin can be improved, and high reliability and thinning are realized.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: March 1, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masanori Minamio, Satoru Konishi, Yoshihiko Morishita, Yuichiro Yamada, Fumito Itoh
  • Patent number: 6856026
    Abstract: A semiconductor chip which does not increase the thickness or the board area of a semiconductor device wherein semiconductor chips are layered and does not increase the wire length between the semiconductor chips even in the case that a plurality of semiconductor chips are layered on a wiring board and a process thereof, as well as a semiconductor device, and the like, are provided.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: February 15, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yuichiro Yamada, Tsuyoshi Hamatani
  • Patent number: 6852374
    Abstract: A liquid crystal display device includes two substrates, a liquid crystal layer sandwiched between the substrates and two alignment films, each being provided on one surface of associated one of the substrates so as to face the liquid crystal layer. The device defines multiple picture elements. At least one of the two alignment films is made of a polymer material that includes a main chain, an atomic group having a bond that is selectively cut when exposed to an actinic ray and a side chain bonded to the main chain via the atomic group. The polymer material with the side chain can give a pretilt angle of greater than 85 degrees but 90 degrees or less to liquid crystal molecules. The polymer material without the side chain can give a pretilt angle of 2 degrees to 15 degrees to the liquid crystal molecules.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: February 8, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masanobu Mizusaki, Tadashi Kawamura, Akiyoshi Fujii, Yuichiro Yamada
  • Publication number: 20040150078
    Abstract: A resin molded type semiconductor device has: a semiconductor chip (12) which is mounted on a die pad portion (11) of a lead frame (9); thin metal wires (14) which connect terminals of the semiconductor chip (12) to inner lead portions (13) of the lead frame (9); and a sealing resin (15), and the lead frame (9) is subjected to an upsetting process so that a supporting portion (11) is located at a position higher than the inner lead portions (13). Since the sealing resin of a thickness corresponding to the step difference of the upsetting exists below the supporting portion, the adhesiveness between the lead frame and the sealing resin can be improved, and high reliability and thinning are realized.
    Type: Application
    Filed: December 31, 2003
    Publication date: August 5, 2004
    Inventors: Masanori Minamio, Satoru Konishi, Yoshihiko Morishita, Yuichiro Yamada, Fumito Itoh
  • Patent number: 6759754
    Abstract: A CF card (1) comprises: a casing constituted by two panel plates (2, 2) and a frame (3); and a printed wiring board (4) accommodated in the casing. A plurality of claw-like engaging parts (5) are provided to the peripheries of the panel plates (2). When the CF card (1) is assembled, the engaging parts (5) of the first panel plate (2) are inserted into through holes of a long groove (8) provided in the frame (3) and then the printed wiring board (4) is mounted on the panel plate (2) located at the inside of the frame (3). Thereafter, the engaging parts (5) of the second panel plate (2) are inserted into the through holes of the long groove (8) from the surface located in the opposite side of the frame (3). There are two types of engaging parts (5): one having lances and the other having holes. Inside the through holes, the lances of the engaging parts (5) of one panel plate (2) are inserted into the holes of the engaging parts (5) of the other panel plate (2).
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: July 6, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Sanwa Denki Kogyo Co., Ltd.
    Inventors: Hirotaka Nishizawa, Hideki Tanaka, Yuichiro Yamada, Tomoaki Kudaishi, Akira Katsumata
  • Publication number: 20040114306
    Abstract: A present invention provides a multi-layer capacitor that can be highly downsized and increased in capacity. A present invention provides a method for manufacturing the multi-layer capacitor including a process of forming a dielectric in the same vacuum chamber, a process of treating a surface of the dielectric, a process of forming a pattern in a metal electrode, a process of forming the metal electrode, and a process of treating a surface of the metal electrode. In this method, etching the dielectric layer flattens a recessed part generated by an electric insulation part.
    Type: Application
    Filed: December 9, 2003
    Publication date: June 17, 2004
    Inventors: Koji Arai, Yuichiro Yamada
  • Patent number: 6714276
    Abstract: A liquid crystal display device comprises: a layer of a chiral liquid crystal material disposed between first and second substrates; and means for applying a voltage across the liquid crystal layer. A first region of the liquid crystal layer is an active region for display and a second region of the liquid crystal layer is a nucleation region for generating a desired liquid crystal state in the first region when a voltage is applied across the liquid crystal layer. The ratio of the thickness d of the liquid crystal layer to the pitch p of the liquid crystal material has a first value (d/p)A in the first region of the liquid crystal layer and has a second value (d/p)N different from the first value in the second region of the liquid crystal layer.
    Type: Grant
    Filed: February 6, 2001
    Date of Patent: March 30, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Michael John Towler, Elizabeth Jane Acosta, Harry Garth Walton, Craig Tombling, Martin David Tillin, Brian Henley, Emma Jayne Walton, Tadashi Kawamura, Akiyoshi Fujii, Yuichiro Yamada
  • Patent number: 6693358
    Abstract: A semiconductor chip which does not increase the thickness or the board area of a semiconductor device wherein semiconductor chips are layered and does not increase the wire length between the semiconductor chips even in the case that a plurality of semiconductor chips are layered on a wiring board and a process thereof, as well as a semiconductor device, and the like, are provided.
    Type: Grant
    Filed: October 10, 2001
    Date of Patent: February 17, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yuichiro Yamada, Tsuyoshi Hamatani
  • Publication number: 20040017012
    Abstract: A semiconductor chip which does not increase the thickness or the board area of a semiconductor device wherein semiconductor chips are layered and does not increase the wire length between the semiconductor chips even in the case that a plurality of semiconductor chips are layered on a wiring board and a process thereof, as well as a semiconductor device, and the like, are provided.
    Type: Application
    Filed: July 11, 2003
    Publication date: January 29, 2004
    Inventors: Yuichiro Yamada, Tsuyoshi Hamatani
  • Publication number: 20040012910
    Abstract: A present invention provides a multi-layer capacitor that can be highly downsized and increased in capacity. A present invention provides a method for manufacturing the multi-layer capacitor including a process of forming a dielectric in the same vacuum chamber, a process of treating a surface of the dielectric, a process of forming a pattern in a metal electrode, a process of forming the metal electrode, and a process of treating a surface of the metal electrode. In this method, etching the dielectric layer flattens a recessed part generated by an electric insulation part.
    Type: Application
    Filed: May 14, 2003
    Publication date: January 22, 2004
    Inventors: Koji Arai, Yuichiro Yamada
  • Patent number: 6650020
    Abstract: The resin-sealed semiconductor device includes a die pad portion, a semiconductor element mounted on the die pad portion and having electrodes, a plurality of lead portions arranged with their respective tips facing the die pad portion, thin metal wires for connecting the electrodes of the semiconductor element to the lead portions, and a sealing resin for sealing the die pad portion, the semiconductor element, the lead portions and connection regions of the thin metal wires except a bottom surface of the die pad portion and respective bottom surfaces and terminal ends of the lead portions. The terminal ends of the lead portions are approximately flush with a side surface of the sealing resin. The die pad portion has a first recess formed in an outer periphery of the bottom surface thereof.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: November 18, 2003
    Assignee: Matsushia Electric Industrial Co., Ltd.
    Inventors: Yuichiro Yamada, Masanori Minamio
  • Publication number: 20030157107
    Abstract: An object of the present invention is to provide a prophylactic or ameliorative agent for insulin resistance and/or obesity based on a new concept, and a screening method therefor.
    Type: Application
    Filed: April 9, 2003
    Publication date: August 21, 2003
    Inventors: Kazumasa Miyawaki, Yuichiro Yamada, Nobuhiro Ban, Yutaka Seino, Yoshiharu Tubamoto, Motohiro Takeda, Hiroyuki Hashimoto, Tokuyuki Yamashita, Takahito Jomori
  • Publication number: 20030123004
    Abstract: The liquid crystal display device of the present invention includes a first substrate, a second substrate placed to face the first substrate, and a liquid crystal layer interposed between the first and second substrates. The liquid crystal layer includes: a splay-aligned region in which a transformation from splay alignment to bend alignment or from bend alignment to splay alignment occurs according to a voltage applied; and a nucleation region serving as a nucleation site for initiating the transformation to occur in the splay-aligned region. The nucleation region includes a plurality of first nucleation regions each extending in a first direction and a plurality of second nucleation regions each extending in a second direction different from the first direction. The splay-aligned region includes a plurality of first splay-aligned regions having a first width in the second direction and a plurality of second splay-aligned regions having a second width smaller than the first width in the second direction.
    Type: Application
    Filed: December 6, 2002
    Publication date: July 3, 2003
    Inventors: Akiyoshi Fujii, Tadashi Kawamura, Yuichiro Yamada
  • Publication number: 20030115748
    Abstract: A CF card (1) comprises: a casing constituted by two panel plates (2, 2) and a frame (3); and a printed wiring board (4) accommodated in the casing. A plurality of claw-like engaging parts (5) are provided to the peripheries of the panel plates (2). When the CF card (1) is assembled, the engaging parts (5) of the first panel plate (2) are inserted into through holes of a long groove (8) provided in the frame (3) and then the printed wiring board (4) is mounted on the panel plate (2) located at the inside of the frame (3). Thereafter, the engaging parts (5) of the second panel plate (2) are inserted into the through holes of the long groove (8) from the surface located in the opposite side of the frame (3). There are two types of engaging parts (5): one having lances and the other having holes. Inside the through holes, the lances of the engaging parts (5) of one panel plate (2) are inserted into the holes of the engaging parts (5) of the other panel plate (2).
    Type: Application
    Filed: February 10, 2003
    Publication date: June 26, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Hirotaka Nishizawa, Hideki Tanaka, Yuichiro Yamada, Tomoaki Kudaishi, Akira Katsumata
  • Publication number: 20030113484
    Abstract: A liquid crystal display device includes two substrates, a liquid crystal layer sandwiched between the substrates and two alignment films, each being provided on one surface of associated one of the substrates so as to face the liquid crystal layer. The device defines multiple picture elements. At least one of the two alignment films is made of a polymer material that includes a main chain, an atomic group having a bond that is selectively cut when exposed to an actinic ray and a side chain bonded to the main chain via the atomic group. The polymer material with the side chain can give a pretilt angle of greater than 85 degrees but 90 degrees or less to liquid crystal molecules. The polymer material without the side chain can give a pretilt angle of 2 degrees to 15 degrees to the liquid crystal molecules.
    Type: Application
    Filed: September 3, 2002
    Publication date: June 19, 2003
    Inventors: Masanobu Mizusaki, Tadashi Kawamura, Akiyoshi Fujii, Yuichiro Yamada
  • Publication number: 20030046345
    Abstract: A project management system is disclosed which is easy to use by members belonging to a project and other persons. The system comprises a server 2 and a DB 3 which stores project by project, contents belonging to those projects participated in by some or all of users. The server 2 comprises a communication controller 4 for transmitting prescribed pages to user terminals 1 and receiving operation messages from the pages, a project desktop sheet generator 10 for reading out contents data from the database 3 in response to those operation messages and generating pages for displaying or accessing all the contents belonging to those projects, project by project, as project desktop sheets, and an access controller 12 for controlling communications with user terminals, when there has been an access made via the communication controller 4 for the content of the contents, in unit of project desktop.
    Type: Application
    Filed: August 1, 2002
    Publication date: March 6, 2003
    Inventors: Makoto Wada, Yuichiro Yamada, Saomi Shimmura
  • Publication number: 20030001289
    Abstract: The resin-sealed semiconductor device includes a die pad portion, a semiconductor element mounted on the die pad portion and having electrodes, a plurality of lead portions arranged with their respective tips facing the die pad portion, thin metal wires for connecting the electrodes of the semiconductor element to the lead portions, and a sealing resin for sealing the die pad portion, the semiconductor element, the lead portions and connection regions of the thin metal wires except a bottom surface of the die pad portion and respective bottom surfaces and terminal ends of the lead portions. The terminal ends of the lead portions are approximately flush with a side surface of the sealing resin.
    Type: Application
    Filed: June 11, 2002
    Publication date: January 2, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yuichiro Yamada, Masanori Minamio
  • Patent number: 6433285
    Abstract: The present invention provides a printed wiring board, an IC card module including the printed wiring board, and a method for fabricating the IC card module, for improving reliability of IC cards. The printed wiring board and the IC card module of the invention include: a base having a resin sealing region, clamped regions in a periphery zone of the resin sealing region clamped with a sealing mold, and non-clamped regions in the periphery zone; and terminals for external connection formed on the top surface of the base. The terminals are formed in a region other than any of the resin sealing region, the clamped regions, and the non-claimed regions.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: August 13, 2002
    Assignee: Matsushita Electronics Corporation
    Inventors: Kenji Maeda, Takashi Takata, Hiroki Naraoka, Hajime Homma, Shigeru Nonoyama, Yoshiyuki Arai, Yuichiro Yamada, Fumito Ito
  • Publication number: 20020047210
    Abstract: A semiconductor chip which does not increase the thickness or the board area of a semiconductor device wherein semiconductor chips are layered and does not increase the wire length between the semiconductor chips even in the case that a plurality of semiconductor chips are layered on a wiring board and a process thereof, as well as a semiconductor device, and the like, are provided.
    Type: Application
    Filed: October 10, 2001
    Publication date: April 25, 2002
    Inventors: Yuichiro Yamada, Tsuyoshi Hamatani