Abstract: The present invention provides an image pickup apparatus which comprises: first and second photoelectric conversion units each including a plurality of photoelectric conversion elements; an image forming unit that forms images viewed from different points on the plurality of photoelectric conversion elements included in each of the first and second photoelectric conversion units; a first holding unit for holding signals from the first photoelectric conversion unit, the first holding unit having at least the same number of capacitors as the number of the photoelectric conversion elements included in the first photoelectric conversion unit; a second holding unit for holding signals from the second photoelectric conversion unit, the second holding unit having at least the same number of capacitors as the number of the photoelectric conversion elements included in the second photoelectric conversion unit; wherein a first common output line to which signals are read out from the plurality of capacitors included in

Abstract: A signal processing apparatus having: a plurality of circuit blocks each circuit block including a signal source and an output transistor adapted to receive a signal generated by the signal source at a control electrode region and output a corresponding signal from a main electrode region; and an analog/digital converter circuit adapted to sequentially process the signal from each of the plurality of circuit blocks, wherein the analog/digital converter circuit includes a reference transistor for receiving a reference level at a control electrode region and outputting a corresponding signal from a main electrode region and a digital output circuit for outputting a digital signal in accordance with a signal output from the output transistor and a signal output from the reference transistor, and wherein the output transistor and reference transistor constitute an input unit of a differential amplifier circuit including the output transistor and reference transistor.

Abstract: A photoelectric conversion apparatus including (A) a semiconductor integrated circuit, for photoelectrically converting an incident optical signal, that includes a first temperature dependent element having a characteristic which exhibits a predetermined change in accordance with a change in temperature and a detection circuit for detecting temperature information, (B) a device arranged outside of the semiconductor integrated circuit, and (C) at least one second temperature dependent element which is arranged inside the device and has a characteristic which exhibits a predetermined change in accordance with a change in temperature. The detection circuit detects temperature information of the first temperature dependent element and temperature information of the at least one second temperature dependent element.

Abstract: A semiconductor circuit assembly is capable of accurately storing a plurality of analog or multi-valued data using circuitry having a small surface area. The circuit assembly includes a first circuit provided in the form of a target memory cell device comprising memory cells which conduct the writing and storage of analog signals. The first circuit has output terminals for outputting stored values to the exterior as voltage signals. Mechanisms supply at least two index voltages. A second circuit performs the function of halting the writing of the analog signals when the output signal at the first circuit output terminals reaches a value representing a desired voltage plus the difference between the two index voltages.

Abstract: A nonvolatile semiconductor memory which is capable of a high degree of integration and can conduct the writing of analog data at high speed and with a high degree of accuracy.The memory device comprises two or more semiconductor devices comprising a first MOS transistor having a first floating gate which is electrically insulated, a first electrode which is capacitively coupled with the first floating gate, a second electrode provided with the first floating gate via a tunnel junction, and a third electrode connected to the second electrode via a switch; the present invention is further provided with a fourth electrode connected commonly with the third electrodes of the semiconductor devices, a fifth electrode connected commonly with the source electrodes of the first MOS transistors, a sixth electrode which is capacitively coupled with the fourth electrode, and a seventh electrode which is connected with the fourth electrode via a switch.

Abstract: A non-volatile semiconductor memory which is capable of high speed and highly accurate analog data writing. The memory includes a first MOS type transistor having a first floating gate which is electrically isolated. A first electrode is capacitively coupled with the first floating gate. A second electrode is connected via a tunnel junction with the first floating gate. A third electrode is capacitively coupled with the second electrode. A second MOS type transistor interconnects the first and second electrodes. A means is provided for applying a predetermined potential difference between the first and third electrodes to thereby cause a tunnel current to flow in the tunnel junction and to store an electric charge in the first floating gate to thereby cause the second MOS type transistor to conduct when the electric charge has reached a predetermined value.