Abstract: A method is provided, including following operations: identifying a first contact via, a second contact via, or a combination thereof in a first standard cell, wherein the first contact via is coupled between a first active region and a first conductive line on a first side, and the second contact via is coupled between a second active region and a second conductive line on a second side; calculating a first cell height according to a first width of the first and second active regions, and calculating a second cell height according to a second width of the first and second active regions; calculating multiple first available cell heights based on a ratio between the first and second cell heights; generating layout designs of multiple first cells; and manufacturing at least first one element in the integrated circuit based on the layout designs of the first cells.

Abstract: A method includes a number of operations. A semiconductor fin is formed and extends from a substrate. A dummy gate structure is formed across the semiconductor fin. An exposed surface of the gate layer is converted into a surface modification layer over the gate layer. Source/drain regions are formed on the semiconductor fin. The dummy gate structure is removed. A gate structure is formed over the semiconductor fin and extends between the source/drain regions and in the surface modification layer.

Abstract: A semiconductor device includes a gate structure on a semiconductor fin, a dielectric layer on the gate structure, and a gate contact extending through the dielectric layer to the gate structure. The gate contact includes a first conductive material on the gate structure, a top surface of the first conductive material extending between sidewalls of the dielectric layer, and a second conductive material on the top surface of the first conductive material.

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

Abstract: The present disclosure provides a semiconductor device, which includes a control circuit, a driving circuit, a voltage pull-up device, and a discharging circuit. The control circuit is coupled between a first terminal and a second terminal of the integrated circuit, and provides a first voltage at a first node. The driving circuit is electrically connected to the control circuit at the first node, and provides a trigger signal at a second node in response to an electrostatic discharge (ESD) event occurring at the first terminal or the second terminal. The voltage pull-up device is coupled between the first terminal and the first node, and configured to pull up the first voltage at the first node in response to the ESD event occurring at the first terminal. The discharging circuit is electrically connected to the second node, and coupled between the first terminal and the second terminal.

Abstract: A self-centering energy dissipation device is adapted to be connected to first and second objects, and includes a first base seat, at least one main shaft, two second base seats and at least one pair of elastic members. The first base seat is adapted to be connected to the first object. The at least one main shaft extends through the first base seat. The second base seats are connected respectively and movably to two opposite ends of the at least one main shaft and are adapted to be connected to the second object. The at least one pair of elastic members are sleeved on the at least one main shaft. Each of the at least one pair of elastic members has a first end abutting against the first base seat, and a second end abutting against a respective one of the second base seats.

Abstract: The present disclosure discloses an inspection device and an inspection method. The inspection device includes a first light source, a second light source, a light source controller and a sensor. The light source controller is configured to enable the first light source to irradiate an object under inspection in a first period of an inspection phase, and to enable the second light source to irradiate the object under inspection in a second period of the inspection phase. The sensor continuously senses the reflected light of the object under inspection in an exposure period of the inspection phase so as to obtain image data of the object under inspection. The exposure period includes the first period and the second period.

Abstract: A computer system for failing a secure boot in a case tampering event comprises a microcontroller unit (MCU); a trusted platform module (TPM), for generating random bytes for a secure boot of the computer system; a bootloader, for storing information comprising the random bytes in the MCU and at least one hardware of the computer system and performing the secure boot, wherein the TPM is comprised in the bootloader; an operating system (OS), for performing the secure boot; and at least one sensor, coupled to the MCU, for detecting a case tampering event, and transmitting a signal for triggering a deletion of the random bytes, if the case tampering event happens. The MCU performs the operation of deleting the random bytes stored in the MCU and the at least one hardware according to a power supply, in response to the signal.

Abstract: A test apparatus has at least one optical source, a high-speed photodetector, a microcontroller or processor, and electrical circuitry to power and drive the optical source, high-speed photodetector, and microcontroller or processor. The apparatus measures the frequency response and optical path length of a multimode optical fiber under test, utilizes a reference VCSEL spatial spectral launch condition and modal-chromatic dispersion interaction data to estimate the channels total modal-chromatic bandwidth of the fiber under test, and computes and presents the estimated maximum data rate the fiber under test can support.

Abstract: The present invention disclose methods for increasing chromium in white kidney bean. The method comprises preparing field, performing a first treatment to the seeds of the white kidney bean, performing a second treatment during the seeding period, performing a third treatment during the flowering period, performing a forth treatment during the fruiting period and performing a fifth treatment during the maturing period. Meanwhile, the amount of chromium in the white kidney bean produced according to the present invention is approximately from 400 to 800 mg/kg.

Abstract: A summer includes a first transconductance amplifier, a first switch coupled to a first input of the summer, a second switch coupled to a second input of the first transconductance amplifier, and a transimpedance amplifier. A first output of the first transconductance amplifier is coupled to a first input of the transimpedance amplifier, and a second output of the first transconductance amplifier is coupled to a second input of the transimpedance amplifier. The summer also includes a second transconductance amplifier. A tap input of the second transconductance amplifier is configured to receive a first digital code indicating a level decision for a first previous symbol, a first output of the second transconductance amplifier is coupled to the first input of the transimpedance amplifier, and a second output of the second transconductance amplifier is coupled to the second input of the transimpedance amplifier.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes forming a transistor over the first wafer; bonding a first wafer to a second wafer; trimming an edge region of the first wafer along a circular trimming path, wherein a center of the circular trimming path is offset from a center of the second wafer in a top view; after trimming the edge region of the first wafer, thinning down the first wafer; and after thinning down the first wafer, forming a backside conductive feature electrically connected to the transistor.

Abstract: An optical fabric includes a plurality of optical waveguides. The fabric has Np input ports with index, X, and Np output ports with index, Y. An interconnection map between input ports, index X, and output ports, index Y is provided by a non-linear function Y=F(X) that satisfies reversible properties given by, F(Y)=X or, X=F(F(X)) or F?1(X)=F(X). The fabric provides full connectivity from any group of M1 adjacent input ports to any group of M2 adjacent output ports where at least one number, M1 or M2 is an even number, and wherein M1×M2=Np.

Abstract: A lock case interlockable with an anti-theft latch is mounted on a door. The lock case includes a latch coupled with a latch hole in a door frame for retaining the door in a closed position. The anti-theft latch can be operated to engage with the door frame. When the latch is picked, the anti-theft latch still remains engaged with the door frame to prevent opening of the door. When normally operated, an inner operating device or an outer operating device can be operated to disengage the latch from the latch hole while disengaging the anti-theft latch from the door frame, permitting easy, convenient opening of the door.

Abstract: A memory device is provided, including at least one bit cell, a pair of transistors, and a voltage generation circuit. The voltage generation circuit is coupled to the negative voltage line and is configured to pull down a voltage of at least one of the pair of data lines to a negative voltage level through the negative voltage line. The voltage generation circuit includes a first capacitive unit, a second capacitive unit, and a switch circuit. The first capacitive unit includes a first capacitor. The second capacitive unit includes a second capacitor. The switch circuit is configured to connect the first capacitor, the second capacitor, or the combination thereof to the negative voltage line in response to a first kick signal and a second kick signal that are different from each other.

Abstract: A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.

Abstract: An amplifier includes a first and a second differential input ports, and a single-ended output port. The amplifier includes a first and a second transistors, each having a gate, source, and drain terminals. The source terminals are coupled to a reference plane and the gate terminals are coupled to the respective first and second differential input ports. The amplifier includes a Balun having a primary and a secondary transformer winding, the primary transformer winding having one end coupled to the drain terminal of the first transistor, an opposite end coupled to the drain terminal of the second transistor, and a center tap coupled to a bias voltage, and the secondary transformer winding is adjacent to the primary transformer winding and having one end coupled to the single-ended output port and an opposite end open circuited. An electromagnetic field generated at the primary induces a signal at the secondary transformer winding.

Abstract: A semiconductor device structure includes a source/drain (S/D) feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a first silicide layer in contact with the first surface of the S/D feature, a second silicide layer opposing the first silicide layer and in contact with the second surface of the S/D feature, a front side S/D contact in contact with the first silicide layer, a back side S/D contact in contact with the second silicide layer, a semiconductor channel layer comprising a sidewall in contact with the sidewall of the source/drain feature, a gate dielectric layer surrounding exposed surfaces of the semiconductor layer, an interlayer dielectric (ILD) disposed adjacent to the gate dielectric layer, and a liner disposed between and in contact with the ILD and the gate dielectric layer.

Abstract: A method for establishing an artificial intelligence prediction model that integrates with a large language model (LLM) in the field of artificial intelligence is provided. The method for establishing the artificial intelligence prediction model includes the creation of the prediction model, obtaining predictions using the model, interpreting the results using SHAP analysis, and leveraging a large language model to overcome the format limitations encountered when dealing with input and output data. A system of an artificial intelligence prediction model is also provided.

Abstract: The present disclosure describes a buried conductive structure in a semiconductor substrate and a method for forming the structure. The structure includes an epitaxial region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer, a first silicide layer disposed within a top portion of the epitaxial region, and a first conductive structure disposed on a top surface of the first silicide layer. The structure further includes a second silicide layer disposed within a bottom portion of the epitaxial region and a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate, where the second conductive structure includes a first metal layer in contact with the second silicide layer and a second metal layer in contact with the first metal layer.