Abstract: A device includes first to third power/ground (PG) elements; a first set of at least three tracks between the first and second PG elements and a second set of at least three tracks between the second and third PG elements, the tracks being arranged in equal numbers between the first and second PG and second and third PG elements; a first row of cells overlapping the first set; and a second row of cells overlapping the second set. In the first row of cells, a first cell has a first height and a second cell has a greater height than the first height; in the second row of cells, a third cell has the first height and a fourth cell has a lesser height less than the first height; and a track configured as an in-cell PG track is aligned with a boundary of the second and fourth cells.

Abstract: An electrical connector includes: an insulating housing having an upper surface, a lower surface, and elongate slots running through the housing; plural rows of first terminals retained in corresponding elongate slots, each of the first terminals comprising a body portion, a transverse portion, an upper elastic arm extending upwardly from the transverse portion and then bending above the body portion, a lower elastic arm extending downwardly from the transverse portion and then bending below the body portion, the transverse portions being connected with corresponding body portions of adjacent first terminals of each row; plural rows of second terminals secured to the housing, wherein a first notch is formed between the lower elastic arm and the body portion of an adjacent first terminal and opens downward, each of the elongate slots defines plural support platforms, and the first notches of each row of first terminals ride on corresponding support platforms.

Abstract: A low-latency free-space optical data communication channel with automatic alignment function has an optical channel, collimators, high reflective screens, and cameras. The optical channel can have two optical lenses designed to facilitate the transmission of an optical signal. The collimators can be integrated with optical fibers and precisely positioned at a focal point of the two optical lenses. Reflective screens, films or tapes encircle both transmitting and receiving lenses. Cameras at each transmitting and receiving terminal are positioned to monitor the optical signal's impact on a lens surface or a high-reflective screen on the opposite side. The cameras use at least one lens to get focused image on a camera sensor and records the optical beam spot impacting the opposite side. Corresponding LED(s) aligned with the lens position on the opposite side allow the computation of the disparity between the optical signal and the lens positioned on the opposite side.

Abstract: This application relates to a method and an apparatus for determining a root-cause defect, and a storage medium. The method includes: obtaining a layout of a chip and diagnosis information of a defect in the chip; determining first feature information based on the layout and the diagnosis information; and determining, based on the first feature information by using a neural network model. With the described technology, both a design defect and a manufacturing defect of a chip can be considered, so that inference for a root cause is more comprehensive. In addition, an interaction relationship between complex root causes can be considered, so that a root-cause defect determined through inference is more accurate. In this way, assistance can be better provided in subsequent improvement of a chip-related design or a manufacturing technique, to reduce an increase in costs caused by a low yield rate.

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Abstract: Some embodiments relate to an integrated circuit (IC) device including a substrate having first photodetector groups respectively associated with a plurality of color pixels and second photodetector groups respectively associated with a plurality of phase detection pixels. Each of the first and second photodetector groups includes one or more photodetectors. The device further includes a grid structure over the substrate, color filters over the substrate, and a crosstalk reduction structure. The grid structure includes light shields, each configured to redirect light away from a corresponding one of the second photodetector groups. Each color filter vertically spans the grid structure at a corresponding one of the first photodetector groups. The crosstalk reduction structure is level with the color filters and limits an amount of the light redirected by the light shield of each of the phase detection pixels to the first photodetector group of a neighboring one of the color pixels.

Abstract: An atomizer for an electronic cigarette includes an atomization compartment housing, an atomizer assembly and an outer cover covering the atomization compartment housing. The outer cover is provided with a suction nozzle opening and a communication hole. The atomization compartment housing includes an atomization cavity, an opening and a through groove. The atomization cavity is disposed inside the atomization compartment housing, and the atomizer assembly is disposed inside the atomization cavity. The opening is disposed at an end of the atomization compartment housing and communicates with the atomization cavity. The opening and the atomization cavity form a smoke passage that communicates with the suction nozzle opening. The through groove is disposed in an outer wall of the atomization compartment housing. The through groove and the outer cover form an intake passage. Two ends of the intake passage communicate with the suction nozzle opening and the communication hole respectively.

Abstract: A memory circuit includes a substrate with a front side and a back side opposite the front side. An interconnect structure is situated on or over the substrate and has first and second metal layers and a via electrically connecting the first and second metal layers. A word line driver circuit is configured to output a word line enable signal to a word line of a memory array. The word line driver circuit has an inverter circuit configured to receive a word line signal, and an enable transistor electrically connected to an output of the inverter circuit by a metal line that includes the first metal layer, the second metal layer, and the via.

Abstract: A hybrid cable designed for providing data communications via both optical fiber and copper wires is provided. The hybrid cable includes internal features for designing a location of the optical fiber and the copper wires relative to each other to optimize cabling characteristics of the hybrid cable.

Abstract: A method of forming an electrode material includes: (1) loading an electrochemically active material onto graphene sheets; (2) combining the electrochemically active material-loaded graphene sheets with holey graphene oxide sheets to form a mixture; and (3) treating the mixture under reducing conditions to form a composite including a graphene framework loaded with the electrochemically active material.

Abstract: A memory operation method, comprising: when a first super block of a memory device is a open block (or in programming state), obtaining a first read count of one of a plurality of first memory blocks in the first super block, wherein the first read count is a number of times that data of one of the first memory blocks is read out; determining whether the first read count is larger than a first threshold; and when the first read count is larger than the first threshold, moving a part of the data in the first super block to a safe area in the memory device, wherein the part of the data comprises data in the first memory block.

Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

Abstract: The charging case includes a cover, a case body and a connection assembly. The case body is provided with a charging recess. The connection assembly includes connection protrusions and a rotation shaft. The connection protrusions are disposed on one of the cover or the case body, and the other of the cover or the case body is provided with a first groove and a second groove. The connection protrusions are rotatably disposed in the first groove, and the connection protrusions are provided with through holes respectively. An end of the rotation shaft passes through a respective though hole. The middle of the rotation shaft is provided with a bump. A part of the middle of the rotation shaft is rotatably disposed in the second groove, where the part of the middle of the rotation shaft is not provided with the bump. The bump is located outside the second groove.

Abstract: A biomimetic turtle includes a trunk, a head movably connected with a front end of the trunk in the front-rear direction, two front limbs disposed on a front section of the trunk and each rotatable relative to the trunk to sway in an up-down direction, and a driving module to drive the head and the front limbs. Each front limb has a curve-shaped rigid portion with a recess, and a deformable flipper portion engaged in the recess and extending rearwardly. With the deformable flipper portion deformed and bent during swaying of the front limbs, a forward propelling force is generated to propel the biomimetic turtle forwardly. The head is operably movable to vary the center of gravity of 10 the biomimetic turtle 100 in the water, and thus the front portion of the biomimetic turtle is inclined upwardly or downwardly to facilitate ascending or descending of the biomimetic turtle.

Abstract: A method of semiconductor fabrication includes forming a plurality of mandrel recesses in a mandrel layer over a hard mask layer, performing a first patterning process on a spacer layer that is deposited over the mandrel layer to form a first opening pattern, performing a second patterning process to etch portions of the mandrel layer to form a second opening pattern, performing a third patterning process to form a third opening pattern in the hard mask layer based on the first opening pattern and the second opening pattern, and forming, through the hard mask layer, metal lines that are in a semiconductor layer under the hard mask layer and that are arranged in a pattern which corresponds to the third opening pattern.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of semiconductor layers vertically stacked over a substrate, wherein the semiconductor layers are vertically spaced apart from each other; forming a source/drain epitaxial structure on sides of the semiconductor layers, wherein the source/drain epitaxial structure is doped with a p-type doping species; implanting fluorine ions into the source/drain epitaxial structure; after implanting fluorine ions into the source/drain epitaxial structure, performing an annealing process to diffuse the p-type doping species into a side region of a topmost one of the semiconductor layers; and forming a source/drain contact over the source/drain epitaxial structure.

Abstract: The present disclosure provides a linear driving apparatus. The linear driving apparatus includes: stators; rotors slidably arranged on the stators; a driving component configured to drive the rotors to slide along an extension direction of the stators; first position feedback units provided with one first position feedback unit provided with a marking signal; and second position feedback units arranged on the stators and spaced apart. The second position feedback units is configured to read position information of the first position feedback units and read the marking signal. The linear driving apparatus in the present disclosure can simplify a manner of identifying the rotor without additional sensors, thereby reducing costs.

Abstract: A method for handling a display control of a microprocessor in an electronic device includes: receiving a display trigger signal; and controlling a panel device in the electronic device to display a content, in response to the display trigger signal; wherein a central processing unit (CPU) in the electronic device is in a power off state, when controlling the panel device to display the content.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes forming a first image sensor element within a first substrate and a second image sensor element within a second substrate. The first image sensor element is configured to generate electrical signals from electromagnetic radiation within a first range of wavelengths and the second image sensor element is configured to generate electrical signals from electromagnetic radiation within a second range of wavelengths. A plurality of deposition processes are performed to form a band-pass filter over the second substrate. The band-pass filter has a plurality of alternating layers of a first material having a first refractive index and a second material having a second refractive index that is less than the first refractive index. The first substrate is bonded to the band-pass filter.